Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #define __SIMPLE_DEVICE__ |
| 19 | |
Damien Zammit | 5680faf | 2016-01-22 22:12:30 +1100 | [diff] [blame] | 20 | #include <cbmem.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 21 | #include <commonlib/helpers.h> |
| 22 | #include <stdint.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 23 | #include <arch/cpu.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 24 | #include <arch/io.h> |
| 25 | #include <device/pci_def.h> |
| 26 | #include <console/console.h> |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 27 | #include <cpu/intel/romstage.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 28 | #include <cpu/x86/mtrr.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 29 | #include <northbridge/intel/x4x/x4x.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 30 | #include <program_loading.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 31 | |
| 32 | /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ |
| 33 | u32 decode_igd_memory_size(const u32 gms) |
| 34 | { |
Arthur Heymans | 27f94ee | 2016-06-18 21:08:58 +0200 | [diff] [blame] | 35 | static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 36 | 32, 48, 64, 128, 256, 96, 160, 224, 352 }; |
| 37 | |
| 38 | if (gms > ARRAY_SIZE(ggc2uma)) |
| 39 | die("Bad Graphics Mode Select (GMS) setting.\n"); |
| 40 | |
| 41 | return ggc2uma[gms] << 10; |
| 42 | } |
| 43 | |
| 44 | /** Decodes used GTT Graphics Memory Size (GGMS) to kilobytes. */ |
| 45 | u32 decode_igd_gtt_size(const u32 gsm) |
| 46 | { |
| 47 | static const u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; |
| 48 | |
| 49 | if (gsm > ARRAY_SIZE(ggc2gtt)) |
| 50 | die("Bad GTT Graphics Memory Size (GGMS) setting.\n"); |
| 51 | |
| 52 | return ggc2gtt[gsm] << 10; |
| 53 | } |
| 54 | |
| 55 | u8 decode_pciebar(u32 *const base, u32 *const len) |
| 56 | { |
| 57 | *base = 0; |
| 58 | *len = 0; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 59 | const pci_devfn_t dev = PCI_DEV(0, 0, 0); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 60 | u32 pciexbar = 0; |
| 61 | u32 pciexbar_reg; |
| 62 | u32 reg32; |
| 63 | int max_buses; |
| 64 | const struct { |
| 65 | u16 num_buses; |
| 66 | u32 addr_mask; |
| 67 | } busmask[] = { |
| 68 | {256, 0xf0000000}, |
| 69 | {128, 0xf8000000}, |
| 70 | {64, 0xfc000000}, |
| 71 | {0, 0}, |
| 72 | }; |
| 73 | |
| 74 | pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); |
| 75 | |
| 76 | if (!(pciexbar_reg & 1)) { |
| 77 | printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); |
| 78 | return 0; |
| 79 | } |
| 80 | |
| 81 | reg32 = (pciexbar_reg >> 1) & 3; |
| 82 | pciexbar = pciexbar_reg & busmask[reg32].addr_mask; |
| 83 | max_buses = busmask[reg32].num_buses; |
| 84 | |
| 85 | if (!pciexbar) { |
| 86 | printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); |
| 87 | return 0; |
| 88 | } |
| 89 | |
| 90 | *base = pciexbar; |
| 91 | *len = max_buses << 20; |
| 92 | return 1; |
| 93 | } |
Damien Zammit | 5680faf | 2016-01-22 22:12:30 +1100 | [diff] [blame] | 94 | |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 95 | /* Depending of UMA and TSEG configuration, TSEG might start at any |
| 96 | * 1 MiB aligment. As this may cause very greedy MTRR setup, push |
| 97 | * CBMEM top downwards to 4 MiB boundary. |
| 98 | */ |
Damien Zammit | 5680faf | 2016-01-22 22:12:30 +1100 | [diff] [blame] | 99 | void *cbmem_top(void) |
| 100 | { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 101 | uintptr_t top_of_ram = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG); |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 102 | top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB); |
| 103 | return (void *) top_of_ram; |
Damien Zammit | 5680faf | 2016-01-22 22:12:30 +1100 | [diff] [blame] | 104 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 105 | |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 106 | #define ROMSTAGE_RAM_STACK_SIZE 0x5000 |
| 107 | |
| 108 | /* setup_stack_and_mtrrs() determines the stack to use after |
| 109 | * cache-as-ram is torn down as well as the MTRR settings to use. */ |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 110 | void *setup_stack_and_mtrrs(void) |
| 111 | { |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 112 | struct postcar_frame pcf; |
| 113 | uintptr_t top_of_ram; |
| 114 | |
| 115 | if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) |
| 116 | die("Unable to initialize postcar frame.\n"); |
| 117 | |
| 118 | /* Cache the ROM as WP just below 4GiB. */ |
Nico Huber | 654cc2f | 2018-05-27 13:52:28 +0200 | [diff] [blame] | 119 | postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 120 | MTRR_TYPE_WRPROT); |
| 121 | |
| 122 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 123 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 124 | |
| 125 | /* Cache two separate 4 MiB regions below the top of ram, this |
| 126 | * satisfies MTRR alignment requirements. If you modify this to |
| 127 | * cover TSEG, make sure UMA region is not set with WRBACK as it |
| 128 | * causes hard-to-recover boot failures. |
| 129 | */ |
| 130 | top_of_ram = (uintptr_t)cbmem_top(); |
| 131 | postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); |
| 132 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); |
| 133 | |
| 134 | /* Save the number of MTRRs to setup. Return the stack location |
| 135 | * pointing to the number of MTRRs. |
| 136 | */ |
| 137 | return postcar_commit_mtrrs(&pcf); |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 138 | } |