blob: 3e78b4f049e75ba46ff3aa9dcdb9841f17297eff [file] [log] [blame]
Simon Glass38d875f2018-04-30 14:08:31 -06001/*
2 * Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge
3 *
4 * This file is part of the coreboot project.
5 *
6 * Copyright 2018 Google LLC.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <console/console.h>
19#include <device/device.h>
20#include <device/path.h>
21#include <device/pci.h>
22#include <device/pci_ids.h>
23#include "chip.h"
24
25enum {
26 BH720_PROTECT = 0xd0,
Simon Glass4f160492018-05-23 15:34:04 -060027 BH720_PROTECT_LOCK_OFF = 0,
28 BH720_PROTECT_LOCK_ON = BIT(0),
Simon Glass38d875f2018-04-30 14:08:31 -060029 BH720_PROTECT_OFF = 0,
Simon Glass4f160492018-05-23 15:34:04 -060030 BH720_PROTECT_ON = BIT(31),
Simon Glass38d875f2018-04-30 14:08:31 -060031
32 BH720_LINK_CTRL = 0x90,
33 BH720_LINK_CTRL_L0_ENABLE = BIT(0),
34 BH720_LINK_CTRL_L1_ENABLE = BIT(1),
35 BH720_LINK_CTRL_CLKREQ = BIT(8),
Simon Glass4f160492018-05-23 15:34:04 -060036
37 BH720_MISC2 = 0xf0,
38 BH720_MISC2_ASPM_DISABLE = BIT(0),
39 BH720_MISC2_APSM_CLKREQ_L1 = BIT(7),
40 BH720_MISC2_APSM_PHY_L1 = BIT(10),
41 BH720_MISC2_APSM_MORE = BIT(12),
42
43 BH720_RTD3_L1 = 0x3e0,
44 BH720_RTD3_L1_DISABLE_L1 = BIT(28),
Simon Glass38d875f2018-04-30 14:08:31 -060045};
46
47static void bh720_init(struct device *dev)
48{
49 struct drivers_generic_bayhub_config *config = dev->chip_info;
50
51 pci_dev_init(dev);
52
53 if (config && config->power_saving) {
54 /*
55 * This procedure for enabling power-saving mode is from the
56 * BayHub BIOS Implementation Guideline document.
57 */
Simon Glass4f160492018-05-23 15:34:04 -060058 pci_write_config32(dev, BH720_PROTECT,
59 BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
Simon Glass38d875f2018-04-30 14:08:31 -060060 pci_or_config32(dev, BH720_RTD3_L1, BH720_RTD3_L1_DISABLE_L1);
61 pci_or_config32(dev, BH720_LINK_CTRL,
62 BH720_LINK_CTRL_L0_ENABLE |
63 BH720_LINK_CTRL_L1_ENABLE);
64 pci_or_config32(dev, BH720_LINK_CTRL, BH720_LINK_CTRL_CLKREQ);
Simon Glass4f160492018-05-23 15:34:04 -060065 pci_update_config32(dev, BH720_MISC2, ~BH720_MISC2_ASPM_DISABLE,
66 BH720_MISC2_APSM_CLKREQ_L1 |
67 BH720_MISC2_APSM_PHY_L1);
68 pci_write_config32(dev, BH720_PROTECT,
69 BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
70
Simon Glass38d875f2018-04-30 14:08:31 -060071 printk(BIOS_INFO, "BayHub BH720: Power-saving enabled (link_ctrl=%#x)\n",
72 pci_read_config32(dev, BH720_LINK_CTRL));
73 }
74}
75
76static struct pci_operations pci_ops = {
77 .set_subsystem = pci_dev_set_subsystem,
78};
79
80static struct device_operations bh720_ops = {
81 .read_resources = pci_dev_read_resources,
82 .set_resources = pci_dev_set_resources,
83 .enable_resources = pci_dev_enable_resources,
84 .ops_pci = &pci_ops,
85 .init = bh720_init,
86};
87
88static const unsigned short pci_device_ids[] = {
89 PCI_DEVICE_ID_O2_BH720,
90 0
91};
92
93static const struct pci_driver bayhub_bh720 __pci_driver = {
94 .ops = &bh720_ops,
95 .vendor = PCI_VENDOR_ID_O2,
96 .devices = pci_device_ids,
97};
98
99static void bh720_enable(struct device *dev)
100{
101 dev->ops = &bh720_ops;
102}
103
104struct chip_operations bayhub_bh720_ops = {
105 CHIP_NAME("BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge")
106 .enable_dev = bh720_enable,
107};