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coreboot
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066e61f3ea1f65012b14467412e6b17351c87dc6
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src
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soc
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intel
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braswell
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smihandler.c
066e61f
soc/intel/braswell: Fix 16-bit read/write PCI_COMMAND register
by Elyes HAOUAS
· 4 years, 4 months ago
ba38f37
soc/intel/braswell: Use SPDX for GPL-2.0-only files
by Angel Pons
· 4 years, 5 months ago
aee7ab2
soc/intel/braswell: Clean up
by Angel Pons
· 4 years, 5 months ago
1c6d8a9
soc: Remove copyright notices
by Patrick Georgi
· 4 years, 5 months ago
aa3b5e29
soc/braswell: hook up smmstore
by Matt DeVillier
· 6 years ago
608fbf8
src/soc/intel: Remove unused <stdlib.h>
by Elyes HAOUAS
· 4 years, 9 months ago
91eb281
soc/intel/braswell: Don't reinitialize SPI after lockdown
by Arthur Heymans
· 4 years, 10 months ago
9dd1a12
ELOG: Introduce elog_gsmi variants
by Kyösti Mälkki
· 4 years, 10 months ago
e31ec29
cpu/x86: Separate save_state struct headers
by Kyösti Mälkki
· 5 years ago
cd49cce
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
by Julius Werner
· 5 years ago
13f6650
device/mmio.h: Add include file for MMIO ops
by Kyösti Mälkki
· 5 years ago
f1b58b7
device/pci: Fix PCI accessor headers
by Kyösti Mälkki
· 5 years ago
d61839c
elog: make elog's SMM handler code follow everything else
by Patrick Georgi
· 6 years ago
c8a649c
src: Use of device_t is deprecated
by Elyes HAOUAS
· 6 years ago
1b6196d
soc/intel/braswell: use common Intel ACPI hardware definitions
by Aaron Durbin
· 8 years ago
97f09c3
soc/braswell: Fix leakage on V1P8S rail
by Shobhit Srivastava
· 9 years ago
2ed0aa2
Correct some common spelling mistakes
by Martin Roth
· 9 years ago
a73b931
tree: drop last paragraph of GPL copyright header
by Patrick Georgi
· 9 years ago
a5d9888
braswell: Tristate CFIO 139 and CFIO 140
by Ravi Sarawadi
· 9 years ago
3247172
Braswell: Add Braswell SOC support
by Lee Leahy
· 9 years ago
25509ee
Remove address from GPLv2 headers
by Patrick Georgi
· 9 years ago
77ff0b1
Braswell: Use Baytrail as Comparison Base
by Lee Leahy
· 9 years ago