Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <arch/io.h> |
| 4 | #include <bootstate.h> |
| 5 | #include <console/console.h> |
| 6 | #include <console/post_codes.h> |
| 7 | #include <cpu/x86/smm.h> |
| 8 | #include <device/mmio.h> |
| 9 | #include <device/pci.h> |
| 10 | #include <intelblocks/lpc_lib.h> |
| 11 | #include <intelblocks/pcr.h> |
| 12 | #include <intelblocks/tco.h> |
| 13 | #include <intelblocks/thermal.h> |
| 14 | #include <soc/p2sb.h> |
| 15 | #include <soc/pci_devs.h> |
| 16 | #include <soc/pcr_ids.h> |
| 17 | #include <soc/pm.h> |
| 18 | #include <soc/smbus.h> |
| 19 | #include <soc/soc_chip.h> |
| 20 | #include <soc/systemagent.h> |
| 21 | #include <spi-generic.h> |
| 22 | |
| 23 | static void pch_finalize(void) |
| 24 | { |
| 25 | uint32_t reg32; |
| 26 | uint8_t *pmcbase; |
| 27 | config_t *config; |
| 28 | uint8_t reg8; |
| 29 | |
| 30 | /* TCO Lock down */ |
| 31 | tco_lockdown(); |
| 32 | |
| 33 | /* TODO: Add Thermal Configuration */ |
| 34 | |
| 35 | /* |
| 36 | * Disable ACPI PM timer based on dt policy |
| 37 | * |
| 38 | * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. |
| 39 | * Disabling ACPI PM timer also switches off TCO |
| 40 | * |
| 41 | * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is |
| 42 | * just required to get to chip config. PCH_DEV_PMC is hidden by this |
| 43 | * point and hence removed from the root bus. pcidev_path_on_root thus |
| 44 | * returns NULL for PCH_DEV_PMC device. |
| 45 | */ |
| 46 | config = config_of_soc(); |
| 47 | pmcbase = pmc_mmio_regs(); |
| 48 | if (config->PmTimerDisabled) { |
| 49 | reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); |
| 50 | reg8 |= (1 << 1); |
| 51 | write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); |
| 52 | } |
| 53 | |
| 54 | /* Disable XTAL shutdown qualification for low power idle. */ |
| 55 | if (config->s0ix_enable) { |
| 56 | reg32 = read32(pmcbase + CPPMVRIC); |
| 57 | reg32 |= XTALSDQDIS; |
| 58 | write32(pmcbase + CPPMVRIC, reg32); |
| 59 | } |
| 60 | |
| 61 | pmc_clear_pmcon_sts(); |
| 62 | } |
| 63 | |
| 64 | static void soc_finalize(void *unused) |
| 65 | { |
| 66 | printk(BIOS_DEBUG, "Finalizing chipset.\n"); |
| 67 | |
| 68 | pch_finalize(); |
| 69 | apm_control(APM_CNT_FINALIZE); |
| 70 | |
| 71 | /* Indicate finalize step with post code */ |
| 72 | post_code(POST_OS_BOOT); |
| 73 | } |
| 74 | |
| 75 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); |
| 76 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); |