Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 2 | |
Kyösti Mälkki | 2787237 | 2021-01-21 16:05:26 +0200 | [diff] [blame] | 3 | #include <acpi/acpi_pm.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 4 | #include <console/console.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 5 | #include <cpu/cpu.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | #include <cpu/intel/microcode.h> |
| 7 | #include <cpu/x86/cr.h> |
| 8 | #include <cpu/x86/msr.h> |
| 9 | #include <device/device.h> |
| 10 | #include <device/pci_def.h> |
| 11 | #include <device/pci_ops.h> |
Aaron Durbin | 789f2b6 | 2015-09-09 17:05:06 -0500 | [diff] [blame] | 12 | #include <fsp/util.h> |
Dinesh Gehlot | ba09eb7 | 2023-01-17 05:06:10 +0000 | [diff] [blame] | 13 | #include <gpio.h> |
Elyes Haouas | def74aa | 2022-10-31 13:44:40 +0100 | [diff] [blame] | 14 | #include <intelblocks/acpi_wake_source.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 15 | #include <soc/lpc.h> |
| 16 | #include <soc/msr.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 17 | #include <soc/pattrs.h> |
| 18 | #include <soc/pci_devs.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 19 | #include <soc/pm.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 20 | #include <soc/ramstage.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 21 | |
| 22 | #define SHOW_PATTRS 1 |
| 23 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 24 | struct pattrs __global_pattrs; |
| 25 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 26 | static void detect_num_cpus(struct pattrs *attrs) |
| 27 | { |
| 28 | int ecx = 0; |
| 29 | |
| 30 | while (1) { |
| 31 | struct cpuid_result leaf_b; |
| 32 | |
| 33 | leaf_b = cpuid_ext(0xb, ecx); |
| 34 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 35 | /* |
| 36 | * The SOC doesn't have hyperthreading so just determine the |
| 37 | * number of cores by from level type (ecx[15:8] == * 2). |
| 38 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 39 | if ((leaf_b.ecx & 0xff00) == 0x0200) { |
| 40 | attrs->num_cpus = leaf_b.ebx & 0xffff; |
| 41 | break; |
| 42 | } |
| 43 | ecx++; |
| 44 | } |
| 45 | } |
| 46 | |
| 47 | static inline void fill_in_msr(msr_t *msr, int idx) |
| 48 | { |
| 49 | *msr = rdmsr(idx); |
| 50 | if (SHOW_PATTRS) { |
| 51 | printk(BIOS_DEBUG, "msr(%x) = %08x%08x\n", |
| 52 | idx, msr->hi, msr->lo); |
| 53 | } |
| 54 | } |
| 55 | |
Elyes HAOUAS | 39303d5 | 2018-07-08 12:40:45 +0200 | [diff] [blame] | 56 | static const char *const stepping_str[] = { |
Frans Hendriks | 83e7324 | 2018-07-13 09:52:04 +0200 | [diff] [blame] | 57 | "A0", "A1", "B0", "B1", "B2", "B3", "C0", "D1" |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 58 | }; |
| 59 | |
| 60 | static void fill_in_pattrs(void) |
| 61 | { |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 62 | struct device *dev; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 63 | msr_t msr; |
| 64 | struct pattrs *attrs = (struct pattrs *)pattrs_get(); |
| 65 | |
| 66 | attrs->cpuid = cpuid_eax(1); |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 67 | dev = pcidev_on_root(LPC_DEV, LPC_FUNC); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 68 | attrs->revid = pci_read_config8(dev, REVID); |
| 69 | /* The revision to stepping IDs have two values per metal stepping. */ |
Elyes HAOUAS | 0bc5d9d | 2022-01-27 07:55:34 +0100 | [diff] [blame] | 70 | if (attrs->revid >= RID_D_STEPPING_START) { |
Frans Hendriks | 83e7324 | 2018-07-13 09:52:04 +0200 | [diff] [blame] | 71 | attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2; |
| 72 | attrs->stepping += STEP_D1; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 73 | |
Elyes HAOUAS | 0bc5d9d | 2022-01-27 07:55:34 +0100 | [diff] [blame] | 74 | } else if (attrs->revid >= RID_C_STEPPING_START) { |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 75 | attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; |
| 76 | attrs->stepping += STEP_C0; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 77 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 78 | } else if (attrs->revid >= RID_B_STEPPING_START) { |
| 79 | attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2; |
| 80 | attrs->stepping += STEP_B0; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 81 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 82 | } else { |
| 83 | attrs->stepping = (attrs->revid - RID_A_STEPPING_START) / 2; |
| 84 | attrs->stepping += STEP_A0; |
| 85 | } |
| 86 | |
| 87 | attrs->microcode_patch = intel_microcode_find(); |
| 88 | attrs->address_bits = cpuid_eax(0x80000008) & 0xff; |
| 89 | detect_num_cpus(attrs); |
| 90 | |
| 91 | if (SHOW_PATTRS) { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 92 | printk(BIOS_DEBUG, "Cpuid %08x cpus %d rid %02x step %s\n", |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 93 | attrs->cpuid, attrs->num_cpus, attrs->revid, |
| 94 | (attrs->stepping >= ARRAY_SIZE(stepping_str)) ? "??" : |
| 95 | stepping_str[attrs->stepping]); |
| 96 | } |
| 97 | |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 98 | fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 99 | fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); |
| 100 | |
| 101 | /* Set IA core speed ratio and voltages */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 102 | fill_in_msr(&msr, MSR_IACORE_RATIOS); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 103 | attrs->iacore_ratios[IACORE_MIN] = (msr.lo >> 0) & 0x7f; |
| 104 | attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 105 | attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 106 | fill_in_msr(&msr, MSR_IACORE_TURBO_RATIOS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 107 | attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ |
| 108 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 109 | fill_in_msr(&msr, MSR_IACORE_VIDS); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 110 | attrs->iacore_vids[IACORE_MIN] = (msr.lo >> 0) & 0x7f; |
| 111 | attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 112 | attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 113 | fill_in_msr(&msr, MSR_IACORE_TURBO_VIDS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 114 | attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ |
| 115 | |
| 116 | /* Set bus clock speed */ |
Subrata Banik | 45a221d | 2015-08-05 17:01:55 +0530 | [diff] [blame] | 117 | attrs->bclk_khz = cpu_bus_freq_khz(); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 118 | } |
| 119 | |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 120 | /* Save wake source information for calculating ACPI _SWS values */ |
Kyösti Mälkki | f67e6751 | 2021-01-22 19:59:07 +0200 | [diff] [blame] | 121 | int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint32_t **gpe0) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 122 | { |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 123 | static uint32_t gpe0_sts; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 124 | |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 125 | *pm1 = ps->pm1_sts & ps->pm1_en; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 126 | |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 127 | gpe0_sts = ps->gpe0_sts & ps->gpe0_en; |
| 128 | *gpe0 = &gpe0_sts; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 129 | |
Duncan Laurie | e73da80 | 2015-09-08 16:16:34 -0700 | [diff] [blame] | 130 | return 1; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 131 | } |
| 132 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 133 | void soc_init_pre_device(struct soc_intel_braswell_config *config) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 134 | { |
| 135 | struct soc_gpio_config *gpio_config; |
| 136 | |
| 137 | fill_in_pattrs(); |
| 138 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 139 | /* Allow for SSE instructions to be executed. */ |
| 140 | write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); |
| 141 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 142 | /* Perform silicon specific init. */ |
| 143 | intel_silicon_init(); |
Hannah Williams | b0eb594 | 2015-08-23 17:24:43 -0700 | [diff] [blame] | 144 | set_max_freq(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 145 | |
| 146 | /* Get GPIO initial states from mainboard */ |
| 147 | gpio_config = mainboard_get_gpios(); |
| 148 | setup_soc_gpios(gpio_config, config->enable_xdp_tap); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 149 | } |