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review.coreboot.org / coreboot / 0359d9dde37b7cce3009cfe630713042601ac5d8 / . / src / soc / intel / tigerlake / finalize.c
blob: 2cc9671c308875220ea3703b80484b65b24a6b7e [file] [log] [blame]
Angel Pons16f6aa82020-04-05 15:47:21 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]2
3/*
4 * This file is created based on Intel Tiger Lake Processor PCH Datasheet
5 * Document number: 575857
6 * Chapter number: 4, 29
7 */
8
9#include <arch/io.h>
10#include <device/mmio.h>
11#include <bootstate.h>
12#include <console/console.h>
13#include <console/post_codes.h>
14#include <cpu/x86/smm.h>
15#include <device/pci.h>
16#include <intelblocks/lpc_lib.h>
17#include <intelblocks/pcr.h>
Subrata Banik0359d9d2020-09-28 18:43:47 +0530[diff] [blame^]18#include <intelblocks/pmclib.h>
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]19#include <intelblocks/tco.h>
20#include <intelblocks/thermal.h>
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]21#include <spi-generic.h>
22#include <soc/p2sb.h>
23#include <soc/pci_devs.h>
24#include <soc/pcr_ids.h>
25#include <soc/pm.h>
26#include <soc/smbus.h>
27#include <soc/soc_chip.h>
28#include <soc/systemagent.h>
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]29
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]30static void pch_finalize(void)
31{
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]32 config_t *config;
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]33
34 /* TCO Lock down */
35 tco_lockdown();
36
Subrata Banik2fff3912020-01-16 10:13:28 +0530[diff] [blame]37 /* TODO: Add Thermal Configuration */
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]38
39 /*
40 * Disable ACPI PM timer based on dt policy
41 *
42 * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
43 * Disabling ACPI PM timer also switches off TCO
44 *
45 * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
46 * just required to get to chip config. PCH_DEV_PMC is hidden by this
47 * point and hence removed from the root bus. pcidev_path_on_root thus
48 * returns NULL for PCH_DEV_PMC device.
49 */
50 config = config_of_soc();
Subrata Banik0359d9d2020-09-28 18:43:47 +0530[diff] [blame^]51 if (config->PmTimerDisabled)
52 pmc_disable_acpi_timer();
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]53
54 /* Disable XTAL shutdown qualification for low power idle. */
Subrata Banik0359d9d2020-09-28 18:43:47 +0530[diff] [blame^]55 if (config->s0ix_enable)
56 pmc_ignore_xtal_shutdown();
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]57
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]58 pmc_clear_pmcon_sts();
59}
60
John Zhao5d16a252020-05-01 22:04:00 -0700[diff] [blame]61static void tbt_finalize(void)
62{
63 int i;
64 const struct device *dev;
65
66 /* Disable Thunderbolt PCIe root ports bus master */
67 for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
68 dev = pcidev_path_on_root(SA_DEVFN_TBT(i));
69 if (dev)
70 pci_dev_disable_bus_master(dev);
71 }
72}
73
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]74static void soc_finalize(void *unused)
75{
76 printk(BIOS_DEBUG, "Finalizing chipset.\n");
77
78 pch_finalize();
Kyösti Mälkkib6585482020-06-01 15:11:14 +0300[diff] [blame]79 apm_control(APM_CNT_FINALIZE);
John Zhao5d16a252020-05-01 22:04:00 -0700[diff] [blame]80 tbt_finalize();
Subrata Banik91e89c52019-11-01 18:30:01 +0530[diff] [blame]81
82 /* Indicate finalize step with post code */
83 post_code(POST_OS_BOOT);
84}
85
86BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
87BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);