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Angel Pons16f6aa82020-04-05 15:47:21 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Subrata Banik91e89c52019-11-01 18:30:01 +05302
3/*
4 * This file is created based on Intel Tiger Lake Processor PCH Datasheet
5 * Document number: 575857
6 * Chapter number: 4, 29
7 */
8
9#include <arch/io.h>
10#include <device/mmio.h>
11#include <bootstate.h>
12#include <console/console.h>
13#include <console/post_codes.h>
14#include <cpu/x86/smm.h>
15#include <device/pci.h>
16#include <intelblocks/lpc_lib.h>
17#include <intelblocks/pcr.h>
18#include <intelblocks/tco.h>
19#include <intelblocks/thermal.h>
20#include <reg_script.h>
21#include <spi-generic.h>
22#include <soc/p2sb.h>
23#include <soc/pci_devs.h>
24#include <soc/pcr_ids.h>
25#include <soc/pm.h>
26#include <soc/smbus.h>
27#include <soc/soc_chip.h>
28#include <soc/systemagent.h>
Subrata Banik91e89c52019-11-01 18:30:01 +053029
Subrata Banik91e89c52019-11-01 18:30:01 +053030static void pch_finalize(void)
31{
32 uint32_t reg32;
33 uint8_t *pmcbase;
34 config_t *config;
35 uint8_t reg8;
36
37 /* TCO Lock down */
38 tco_lockdown();
39
Subrata Banik2fff3912020-01-16 10:13:28 +053040 /* TODO: Add Thermal Configuration */
Subrata Banik91e89c52019-11-01 18:30:01 +053041
42 /*
43 * Disable ACPI PM timer based on dt policy
44 *
45 * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
46 * Disabling ACPI PM timer also switches off TCO
47 *
48 * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
49 * just required to get to chip config. PCH_DEV_PMC is hidden by this
50 * point and hence removed from the root bus. pcidev_path_on_root thus
51 * returns NULL for PCH_DEV_PMC device.
52 */
53 config = config_of_soc();
54 pmcbase = pmc_mmio_regs();
55 if (config->PmTimerDisabled) {
56 reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
57 reg8 |= (1 << 1);
58 write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
59 }
60
61 /* Disable XTAL shutdown qualification for low power idle. */
62 if (config->s0ix_enable) {
63 reg32 = read32(pmcbase + CPPMVRIC);
64 reg32 |= XTALSDQDIS;
65 write32(pmcbase + CPPMVRIC, reg32);
66 }
67
Subrata Banik91e89c52019-11-01 18:30:01 +053068 pmc_clear_pmcon_sts();
69}
70
71static void soc_finalize(void *unused)
72{
73 printk(BIOS_DEBUG, "Finalizing chipset.\n");
74
75 pch_finalize();
Kyösti Mälkkib6585482020-06-01 15:11:14 +030076 apm_control(APM_CNT_FINALIZE);
Subrata Banik91e89c52019-11-01 18:30:01 +053077
78 /* Indicate finalize step with post code */
79 post_code(POST_OS_BOOT);
80}
81
82BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
83BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);