Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2 | |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 3 | #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ |
| 4 | #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 5 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 6 | #define DEFAULT_HECIBAR ((u8 *)0xfed17000) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 7 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 8 | #define IOMMU_BASE1 0xfed90000 |
| 9 | #define IOMMU_BASE2 0xfed91000 |
| 10 | #define IOMMU_BASE3 0xfed92000 |
| 11 | #define IOMMU_BASE4 0xfed93000 |
| 12 | |
| 13 | /* |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 14 | * D1:F0 PEG |
| 15 | */ |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 16 | #define PEG_CAP 0xa2 |
| 17 | #define SLOTCAP 0xb4 |
| 18 | #define PEGLC 0xec |
| 19 | #define D1F0_VCCAP 0x104 |
| 20 | #define D1F0_VC0RCTL 0x114 |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 21 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 22 | /* Chipset types */ |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 23 | #define IRONLAKE_MOBILE 0 |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 24 | #define IRONLAKE_DESKTOP 1 |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 25 | #define IRONLAKE_SERVER 2 |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 26 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 27 | /* Northbridge BARs */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 28 | #ifndef __ACPI__ |
| 29 | #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ |
| 30 | #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ |
| 31 | #else |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 32 | #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ |
| 33 | #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 34 | #endif |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 35 | #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 36 | |
| 37 | #define QUICKPATH_BUS 0xff |
| 38 | |
| 39 | #include <southbridge/intel/ibexpeak/pch.h> |
| 40 | |
| 41 | /* Everything below this line is ignored in the DSDT */ |
| 42 | #ifndef __ACPI__ |
| 43 | |
| 44 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
| 45 | |
Angel Pons | 35a7742 | 2020-09-15 00:31:26 +0200 | [diff] [blame] | 46 | #include "registers/host_bridge.h" |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 47 | |
Angel Pons | e9d1d70 | 2020-07-22 12:47:00 +0200 | [diff] [blame] | 48 | /* |
Angel Pons | c642a0d | 2020-07-22 18:21:43 +0200 | [diff] [blame] | 49 | * Generic Non-Core Registers |
| 50 | */ |
| 51 | #define QPI_NON_CORE PCI_DEV(QUICKPATH_BUS, 0, 0) |
| 52 | |
Angel Pons | 9addda3 | 2020-07-22 18:37:32 +0200 | [diff] [blame] | 53 | #define MAX_RTIDS 0x60 |
| 54 | #define DESIRED_CORES 0x80 |
| 55 | #define MIRROR_PORT_CTL 0xd0 |
| 56 | |
Angel Pons | c642a0d | 2020-07-22 18:21:43 +0200 | [diff] [blame] | 57 | /* |
Angel Pons | 3ab19b3 | 2020-07-22 16:29:54 +0200 | [diff] [blame] | 58 | * SAD - System Address Decoder |
Angel Pons | e9d1d70 | 2020-07-22 12:47:00 +0200 | [diff] [blame] | 59 | */ |
Angel Pons | 3ab19b3 | 2020-07-22 16:29:54 +0200 | [diff] [blame] | 60 | #define QPI_SAD PCI_DEV(QUICKPATH_BUS, 0, 1) |
| 61 | |
Angel Pons | e9d1d70 | 2020-07-22 12:47:00 +0200 | [diff] [blame] | 62 | #define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ |
Vladimir Serbinenko | 786c0f5 | 2014-01-02 10:16:46 +0100 | [diff] [blame] | 63 | #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 64 | |
Angel Pons | 4500893 | 2020-07-22 16:43:48 +0200 | [diff] [blame] | 65 | #define SAD_PCIEXBAR 0x50 |
| 66 | |
Angel Pons | 6757337 | 2020-07-22 16:56:00 +0200 | [diff] [blame] | 67 | #define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */ |
| 68 | #define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */ |
| 69 | |
Angel Pons | 93d9517 | 2020-07-22 17:30:49 +0200 | [diff] [blame] | 70 | /* |
| 71 | * QPI Link 0 |
| 72 | */ |
| 73 | #define QPI_LINK_0 PCI_DEV(QUICKPATH_BUS, 2, 0) |
| 74 | |
Angel Pons | 0814357 | 2020-07-22 17:47:06 +0200 | [diff] [blame] | 75 | #define QPI_QPILCP 0x40 /* QPI Link Capability */ |
| 76 | #define QPI_QPILCL 0x48 /* QPI Link Control */ |
| 77 | #define QPI_QPILS 0x50 /* QPI Link Status */ |
| 78 | #define QPI_DEF_RMT_VN_CREDITS 0x58 /* Default Available Remote Credits */ |
| 79 | |
Angel Pons | 10993c4 | 2020-07-22 17:49:28 +0200 | [diff] [blame] | 80 | /* |
| 81 | * QPI Physical Layer 0 |
| 82 | */ |
| 83 | #define QPI_PHY_0 PCI_DEV(QUICKPATH_BUS, 2, 1) |
| 84 | |
Angel Pons | a457e35 | 2020-07-22 18:17:33 +0200 | [diff] [blame] | 85 | #define QPI_PLL_STATUS 0x50 |
| 86 | #define QPI_PLL_RATIO 0x54 |
| 87 | #define QPI_PHY_CAPABILITY 0x68 /* QPI Phys. Layer Capability */ |
| 88 | #define QPI_PHY_CONTROL 0x6c /* QPI Phys. Layer Control */ |
| 89 | #define QPI_PHY_INIT_STATUS 0x80 /* QPI Phys. Layer Initialization Status */ |
| 90 | #define QPI_PHY_PRIM_TIMEOUT 0x94 /* QPI Phys. Layer Primary Timeout Value */ |
| 91 | #define QPI_PHY_PWR_MGMT 0xd0 /* QPI Phys. Layer Power Management */ |
| 92 | #define QPI_PHY_EP_SELECT 0xe0 /* QPI Phys. Layer Electrical Parameter Select */ |
| 93 | #define QPI_PHY_EP_MCTR 0xf4 /* QPI Phys. Layer Electrical Parameter Misc. Control */ |
| 94 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 95 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
| 96 | |
| 97 | #define MSAC 0x62 /* Multi Size Aperture Control */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 98 | |
| 99 | /* |
| 100 | * MCHBAR |
| 101 | */ |
| 102 | |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 103 | #define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) |
| 104 | #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) |
| 105 | #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) |
| 106 | #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) |
| 107 | #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) |
| 108 | #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) |
| 109 | #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) |
| 110 | #define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) |
| 111 | #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) |
| 112 | #define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) |
| 113 | #define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) |
| 114 | #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 115 | /* |
| 116 | * EPBAR - Egress Port Root Complex Register Block |
| 117 | */ |
| 118 | |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 119 | #define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) |
| 120 | #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) |
| 121 | #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 122 | |
Angel Pons | 5876998 | 2020-09-15 00:36:15 +0200 | [diff] [blame] | 123 | #include "registers/epbar.h" |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 124 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 125 | /* |
| 126 | * DMIBAR |
| 127 | */ |
| 128 | |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 129 | #define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) |
| 130 | #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) |
| 131 | #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 132 | |
Angel Pons | 5876998 | 2020-09-15 00:36:15 +0200 | [diff] [blame] | 133 | #include "registers/dmibar.h" |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 134 | |
| 135 | #ifndef __ASSEMBLER__ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 136 | |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 137 | void intel_ironlake_finalize_smm(void); |
Kyösti Mälkki | 82c0e7e | 2019-11-05 19:06:56 +0200 | [diff] [blame] | 138 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 139 | int bridge_silicon_revision(void); |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 140 | void ironlake_early_initialization(int chipset_type); |
| 141 | void ironlake_late_initialization(void); |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 142 | void mainboard_pre_raminit(void); |
| 143 | void mainboard_get_spd_map(u8 *spd_addrmap); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 144 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 145 | #endif |
| 146 | #endif |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 147 | #endif /* __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ */ |