blob: 28f312179e5e7ed75a4211623cd706be66bf7416 [file] [log] [blame]
Patrick Georgi02363b52020-05-05 20:48:50 +02001/* This file is part of the coreboot project. */
Mariusz Szafranskia4041332017-08-02 17:28:17 +02002/*
Mariusz Szafranskia4041332017-08-02 17:28:17 +02003 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
Mariusz Szafranskia4041332017-08-02 17:28:17 +020015#include <bootblock_common.h>
16#include <cpu/x86/mtrr.h>
17#include <device/pci.h>
18#include <FsptUpd.h>
19#include <intelblocks/fast_spi.h>
Mariusz Szafranskia4041332017-08-02 17:28:17 +020020#include <soc/bootblock.h>
21#include <soc/iomap.h>
22#include <spi-generic.h>
Mariusz Szafranskia4041332017-08-02 17:28:17 +020023#include <console/console.h>
24
25const FSPT_UPD temp_ram_init_params = {
26 .FspUpdHeader = {
27 .Signature = 0x545F445055564E44ULL,
28 .Revision = 1,
29 .Reserved = {0},
30 },
31 .FsptCoreUpd = {
Subrata Banik24ab1c52019-11-25 11:57:28 +053032 /*
33 * It is a requirement for firmware to have Firmware Interface Table
34 * (FIT), which contains pointers to each microcode update.
35 * The microcode update is loaded for all logical processors before
36 * cpu reset vector.
37 *
38 * All SoC since Gen-4 has above mechanism in place to load microcode
39 * even before hitting CPU reset vector. Hence skipping FSP-T loading
40 * microcode after CPU reset by passing '0' value to
41 * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
42 */
43 .MicrocodeRegionBase = 0,
44 .MicrocodeRegionLength = 0,
Mariusz Szafranskia4041332017-08-02 17:28:17 +020045 .CodeRegionBase =
Arthur Heymans62c0b612019-02-05 21:10:01 +010046 (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE),
47 .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE,
Mariusz Szafranskia4041332017-08-02 17:28:17 +020048 .Reserved1 = {0},
49 },
50 .FsptConfig = {
51 .PcdFsptPort80RouteDisable = 0,
52 .ReservedTempRamInitUpd = {0},
53 },
54 .UnusedUpdSpace0 = {0},
55 .UpdTerminator = 0x55AA,
56};
57
58asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
59{
60 /* Call lib/bootblock.c main */
Kyösti Mälkki101ef0b2019-08-18 06:58:42 +030061 bootblock_main_with_basetime(base_timestamp);
Mariusz Szafranskia4041332017-08-02 17:28:17 +020062};
63
64void bootblock_soc_early_init(void)
65{
66
Julius Wernercd49cce2019-03-05 16:53:33 -080067#if (CONFIG(CONSOLE_SERIAL))
Mariusz Szafranskia4041332017-08-02 17:28:17 +020068 early_uart_init();
69#endif
70};
71
72void bootblock_soc_init(void)
73{
Julius Wernercd49cce2019-03-05 16:53:33 -080074 if (CONFIG(BOOTBLOCK_CONSOLE))
Mariusz Szafranskia4041332017-08-02 17:28:17 +020075 printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");
76};