Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 20 | #include <stdint.h> |
| 21 | #include <arch/cpu.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <arch/romcc_io.h> |
| 24 | #include <console/console.h> |
| 25 | #include <cpu/x86/msr.h> |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 26 | #include "sr5650.h" |
| 27 | #include "cmn.h" |
| 28 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 29 | /* space = 0: AX_INDXC, AX_DATAC |
| 30 | * space = 1: AX_INDXP, AX_DATAP |
| 31 | */ |
| 32 | static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val) |
| 33 | { |
| 34 | u32 tmp; |
| 35 | |
| 36 | /* read axindc to tmp */ |
| 37 | outl(space << 30 | space << 3 | 0x30, AB_INDX); |
| 38 | outl(axindc, AB_DATA); |
| 39 | outl(space << 30 | space << 3 | 0x34, AB_INDX); |
| 40 | tmp = inl(AB_DATA); |
| 41 | |
| 42 | tmp &= ~mask; |
| 43 | tmp |= val; |
| 44 | |
| 45 | /* write tmp */ |
| 46 | outl(space << 30 | space << 3 | 0x30, AB_INDX); |
| 47 | outl(axindc, AB_DATA); |
| 48 | outl(space << 30 | space << 3 | 0x34, AB_INDX); |
| 49 | outl(tmp, AB_DATA); |
| 50 | } |
| 51 | |
| 52 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 53 | /* family 10 only, for reg > 0xFF */ |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 54 | #if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 55 | static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask, |
| 56 | u32 val) |
| 57 | { |
| 58 | u32 reg_old, reg; |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 59 | reg = reg_old = pci_read_config32(fam10_dev, reg_pos); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 60 | reg &= ~mask; |
| 61 | reg |= val; |
| 62 | if (reg != reg_old) { |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 63 | pci_write_config32(fam10_dev, reg_pos, reg); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 64 | } |
| 65 | } |
| 66 | #else |
| 67 | #define set_fam10_ext_cfg_enable_bits(a, b, c, d) do {} while (0) |
| 68 | #endif |
| 69 | |
| 70 | |
| 71 | /* |
| 72 | * Compliant with CIM_33's ATINB_PrepareInit |
| 73 | */ |
| 74 | static void get_cpu_rev(void) |
| 75 | { |
| 76 | u32 eax; |
| 77 | |
| 78 | eax = cpuid_eax(1); |
| 79 | printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax); |
| 80 | if (eax <= 0xfff) |
| 81 | printk(BIOS_INFO, "CPU Rev is K8_Cx.\n"); |
| 82 | else if (eax <= 0x10fff) |
| 83 | printk(BIOS_INFO, "CPU Rev is K8_Dx.\n"); |
| 84 | else if (eax <= 0x20fff) |
| 85 | printk(BIOS_INFO, "CPU Rev is K8_Ex.\n"); |
| 86 | else if (eax <= 0x40fff) |
| 87 | printk(BIOS_INFO, "CPU Rev is K8_Fx.\n"); |
| 88 | else if (eax == 0x60fb1 || eax == 0x60f81) /*These two IDS are exception, they are G1. */ |
| 89 | printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); |
| 90 | else if (eax <= 0X60FF0) |
| 91 | printk(BIOS_INFO, "CPU Rev is K8_G0.\n"); |
| 92 | else if (eax <= 0x100000) |
| 93 | printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); |
| 94 | else if (eax <= 0x100f00) |
| 95 | printk(BIOS_INFO, "CPU Rev is Fam 10.\n"); |
| 96 | else |
| 97 | printk(BIOS_INFO, "CPU Rev is not recognized.\n"); |
| 98 | } |
| 99 | |
| 100 | /* |
| 101 | CIM NB_GetRevisionInfo() |
| 102 | */ |
| 103 | static u8 get_nb_rev(device_t nb_dev) |
| 104 | { |
| 105 | u8 reg; |
| 106 | reg = pci_read_config8(nb_dev, 0x8); /* copy from CIM, can't find in doc */ |
| 107 | switch(reg & 3) |
| 108 | { |
| 109 | case 0x00: |
| 110 | reg = REV_SR5650_A11; |
| 111 | break; |
| 112 | case 0x02: |
| 113 | default: |
| 114 | reg = REV_SR5650_A12; |
| 115 | break; |
| 116 | } |
| 117 | return reg; |
| 118 | } |
| 119 | |
| 120 | /***************************************** |
| 121 | * Compliant with SR5650_CIMX_4_5_0 NBHT_InitHT(). |
| 122 | * Init HT link speed/width for sr5650 -- k8 link |
| 123 | 1: Check CPU Family, Family10? |
| 124 | 2: Get CPU's HT speed and width |
| 125 | 3: Decide HT mode 1 or 3 by HT Speed. >1GHz: HT3, else HT1 |
| 126 | 4: |
| 127 | *****************************************/ |
| 128 | static const u8 sr5650_ibias[] = { |
| 129 | /* 1, 3 are reserved. */ |
| 130 | [0x0] = 0x44, /* 200Mhz HyperTransport 1 only */ |
| 131 | [0x2] = 0x44, /* 400Mhz HyperTransport 1 only */ |
| 132 | [0x4] = 0xB6, /* 600Mhz HyperTransport 1 only */ |
| 133 | [0x5] = 0x44, /* 800Mhz HyperTransport 1 only */ |
| 134 | [0x6] = 0x96, /* 1Ghz HyperTransport 1 only */ |
| 135 | /* HT3 for Family 10 */ |
| 136 | [0x7] = 0xB6, /* 1.2Ghz HyperTransport 3 only */ |
| 137 | [0x8] = 0x23, /* 1.4Ghz HyperTransport 3 only */ |
| 138 | [0x9] = 0x44, /* 1.6Ghz HyperTransport 3 only */ |
| 139 | [0xa] = 0x64, /* 1.8Ghz HyperTransport 3 only */ |
| 140 | [0xb] = 0x96, /* 2.0Ghz HyperTransport 3 only */ |
| 141 | [0xc] = 0xA6, /* 2.2Ghz HyperTransport 3 only */ |
| 142 | [0xd] = 0xB6, /* 2.4Ghz HyperTransport 3 only */ |
| 143 | [0xe] = 0xC6, /* 2.6Ghz HyperTransport 3 only */ |
| 144 | }; |
| 145 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 146 | void sr5650_htinit(void) |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 147 | { |
| 148 | /* |
| 149 | * About HT, it has been done in enumerate_ht_chain(). |
| 150 | */ |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 151 | device_t cpu_f0, sr5650_f0, clk_f1; |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 152 | u32 reg; |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 153 | u8 cpu_ht_freq, cpu_htfreq_max, ibias; |
| 154 | u8 sbnode; |
| 155 | u8 sblink; |
| 156 | u16 linkfreq_reg; |
| 157 | u16 linkfreqext_reg; |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 158 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 159 | /************************ |
| 160 | * get cpu's ht freq, in cpu's function 0, offset 0x88 |
| 161 | * bit11-8, specifics the maximum operation frequency of the link's transmitter clock. |
| 162 | * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero |
| 163 | * value to this reg, and that value takes effect on the next warm reset or |
| 164 | * LDTSTOP_L disconnect sequence. |
| 165 | * please see the table sr5650_ibias about the value and its corresponding frequency. |
| 166 | ************************/ |
| 167 | /* Link0, Link1 are for connection between P0 and P1. |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 168 | * TODO: Check the topology of the MP and NB. Or we just read the nbconfig? */ |
| 169 | /* NOTE: In most cases, we only have one CPU. In that case, we should read 0x88. */ |
| 170 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 171 | /* Find out the node ID and the Link ID that |
| 172 | * connects to the Southbridge (system IO hub). |
| 173 | */ |
| 174 | sbnode = (pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60) >> 8) & 7; |
| 175 | sblink = (pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64) >> 8) & 3; /* bit[10] sublink, bit[9,8] link. */ |
| 176 | cpu_f0 = PCI_DEV(0, (0x18 + sbnode), 0); |
| 177 | |
| 178 | /* |
| 179 | * link freq reg of Link0, 1, 2, 3 is 0x88, 0xA8, 0xC8, 0xE8 respectively |
| 180 | * link freq ext reg of Link0, 1, 2, 3 is 0x9C, 0xBC, 0xDC, 0xFC respectively |
| 181 | */ |
| 182 | linkfreq_reg = 0x88 + (sblink << 5); |
| 183 | linkfreqext_reg = 0x9C + (sblink << 5); |
| 184 | reg = pci_read_config32(cpu_f0, linkfreq_reg); |
| 185 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 186 | cpu_ht_freq = (reg & 0xf00) >> 8; |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 187 | |
| 188 | /* Freq[4] is only valid for revision D and later processors */ |
| 189 | if (cpuid_eax(1) >= 0x100F80) { |
| 190 | cpu_htfreq_max = 0x14; |
| 191 | cpu_ht_freq |= ((pci_read_config32(cpu_f0, linkfreqext_reg) & 0x01) << 4); |
| 192 | } else { |
| 193 | cpu_htfreq_max = 0x0F; |
| 194 | } |
| 195 | |
| 196 | printk(BIOS_INFO, "sr5650_htinit: Node %x Link %x, HT freq=%x.\n", |
| 197 | sbnode, sblink, cpu_ht_freq); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 198 | sr5650_f0 = PCI_DEV(0, 0, 0); |
| 199 | |
| 200 | clk_f1 = PCI_DEV(0, 0, 1); /* We need to make sure the F1 is accessible. */ |
| 201 | |
| 202 | ibias = sr5650_ibias[cpu_ht_freq]; |
| 203 | |
| 204 | /* If HT freq>1GHz, we assume the CPU is fam10, else it is K8. |
| 205 | * Is it appropriate? |
| 206 | * Frequency is 1GHz, i.e. cpu_ht_freq is 6, in most cases. |
| 207 | * So we check 6 only, it would be faster. */ |
| 208 | if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) || |
| 209 | (cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) { |
| 210 | printk(BIOS_INFO, "sr5650_htinit: HT1 mode\n"); |
| 211 | |
| 212 | /* HT1 mode, RPR 5.4.2 */ |
| 213 | /* set IBIAS code */ |
| 214 | set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias); |
| 215 | /* Optimizes chipset HT transmitter drive strength */ |
| 216 | set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3, 0x3); |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 217 | } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < cpu_htfreq_max)) { |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 218 | printk(BIOS_INFO, "sr5650_htinit: HT3 mode\n"); |
| 219 | |
| 220 | /* Enable Protocol checker */ |
| 221 | set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC); |
| 222 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 223 | #if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) /* save some spaces */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 224 | /* HT3 mode, RPR 5.4.3 */ |
| 225 | set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0); |
| 226 | |
| 227 | /* set IBIAS code */ |
| 228 | set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias); |
| 229 | /* Optimizes chipset HT transmitter drive strength */ |
| 230 | set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3, 0x1); |
| 231 | /* Enables error-retry mode */ |
| 232 | set_nbcfg_enable_bits(sr5650_f0, 0x44, 0x1, 0x1); |
| 233 | /* Enables scrambling and Disalbes command throttling */ |
| 234 | set_nbcfg_enable_bits(sr5650_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14)); |
| 235 | /* Enables transmitter de-emphasis */ |
| 236 | set_nbcfg_enable_bits(sr5650_f0, 0xa4, 1 << 31, 1 << 31); |
| 237 | /* Enabels transmitter de-emphasis level */ |
| 238 | /* Sets training 0 time */ |
| 239 | set_nbcfg_enable_bits(sr5650_f0, 0xa0, 0x3F, 0x14); |
| 240 | |
| 241 | /* Enables strict TM4 detection */ |
| 242 | set_htiu_enable_bits(sr5650_f0, 0x15, 0x1 << 22, 0x1 << 22); |
| 243 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 244 | /* Optimizes chipset HT transmitter drive strength */ |
| 245 | set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3 << 0, 0x1 << 0); |
| 246 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 247 | /* HyperTransport 3 Processor register settings to be done in northbridge */ |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 248 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 249 | /* Enables error-retry mode */ |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 250 | set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130 + (sblink << 2), 1 << 0, 1 << 0); |
| 251 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 252 | /* Enables scrambling */ |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 253 | set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170 + (sblink << 2), 1 << 3, 1 << 3); |
| 254 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 255 | /* Enables transmitter de-emphasis |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 256 | * This depends on the PCB design and the trace |
| 257 | */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 258 | /* Disables command throttling */ |
| 259 | set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10); |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 260 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 261 | /* Sets Training 0 Time. See T0Time table for encodings */ |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 262 | /* AGESA have set it to recommanded value already |
| 263 | * The recommended values are 14h(2us) if F0x[18C:170][LS2En]=0 |
| 264 | * and 26h(12us) if F0x[18C:170][LS2En]=1 |
| 265 | */ |
| 266 | //set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x26); |
| 267 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 268 | /* HT Buffer Allocation for Ganged Links!!! */ |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 269 | #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 270 | } |
| 271 | } |
| 272 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 273 | #if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) /* save some spaces */ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 274 | void fam10_optimization(void) |
| 275 | { |
| 276 | device_t cpu_f0, cpu_f2, cpu_f3; |
| 277 | device_t cpu1_f0, cpu1_f2, cpu1_f3; |
| 278 | msr_t msr; |
| 279 | u32 val; |
| 280 | |
| 281 | printk(BIOS_INFO, "fam10_optimization()\n"); |
| 282 | msr = rdmsr(0xC001001F); |
| 283 | msr.hi |= 1 << 14; /* bit 46: EnableCf8ExtCfg */ |
| 284 | wrmsr(0xC001001F, msr); |
| 285 | |
| 286 | cpu_f0 = PCI_DEV(0, 0x18, 0); |
| 287 | cpu_f2 = PCI_DEV(0, 0x18, 2); |
| 288 | cpu_f3 = PCI_DEV(0, 0x18, 3); |
| 289 | cpu1_f0 = PCI_DEV(0, 0x19, 0); |
| 290 | cpu1_f2 = PCI_DEV(0, 0x19, 2); |
| 291 | cpu1_f3 = PCI_DEV(0, 0x19, 3); |
| 292 | |
| 293 | val = pci_read_config32(cpu1_f3, 0x8C); |
| 294 | val |= 1 << 14; |
| 295 | pci_write_config32(cpu1_f3, 0x8C, val); |
| 296 | |
| 297 | /* TODO: HT Buffer Allocation for (un)Ganged Links */ |
| 298 | /* rpr Table 5-11, 5-12 */ |
| 299 | } |
| 300 | #else |
| 301 | #define fam10_optimization() do{}while(0) |
| 302 | #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ |
| 303 | |
| 304 | /***************************************** |
| 305 | * Compliant with CIM_33's ATINB_PCICFG_POR_TABLE |
| 306 | *****************************************/ |
| 307 | static void sr5650_por_pcicfg_init(device_t nb_dev) |
| 308 | { |
| 309 | /* enable PCI Memory Access */ |
| 310 | set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02); |
| 311 | |
| 312 | set_nbcfg_enable_bits(nb_dev, 0x14, ~0, 0x0); |
| 313 | set_nbcfg_enable_bits(nb_dev, 0x18, ~0, 0x0); |
| 314 | set_nbcfg_enable_bits(nb_dev, 0x20, ~0, 0x0); |
| 315 | set_nbcfg_enable_bits(nb_dev, 0x84, ~0, 0x03000010); |
| 316 | |
| 317 | /* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge |
| 318 | * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation |
| 319 | * BMMsgEn */ |
| 320 | set_nbcfg_enable_bits(nb_dev, 0x4C, (u8)(~0x00), 0x52042); |
| 321 | |
| 322 | set_nbcfg_enable_bits(nb_dev, 0x7C, (u8)(~0), 0x0); |
| 323 | |
| 324 | /* Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR, |
| 325 | * force this BAR as mem type in sr5650_gfx.c */ |
| 326 | //set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03); |
| 327 | } |
| 328 | |
| 329 | /***************************************** |
| 330 | * Compliant with CIM_33's ATINB_MISCIND_POR_TABLE |
| 331 | * Compliant with CIM_33's MISC_INIT_TBL |
| 332 | *****************************************/ |
| 333 | static void sr5650_por_misc_index_init(device_t nb_dev) |
| 334 | { |
| 335 | /* disable IOMMU */ |
| 336 | set_nbmisc_enable_bits(nb_dev, 0x75, 0x1, 0x0); |
| 337 | /* NBMISCIND:0x75[29]= 1 Device ID for hotplug and PME message */ |
| 338 | set_nbmisc_enable_bits(nb_dev, 0x75, 1 << 29, 1 << 29); |
| 339 | set_nbmisc_enable_bits(nb_dev, 0x75, 1 << 9, 1 << 9); /* no doc reference, comply with BTS */ |
| 340 | set_nbmisc_enable_bits(nb_dev, 0x46, 1 << 7, 1 << 7); /* bit7 BTS fail*/ |
| 341 | /*P2P*/ |
| 342 | set_nbmisc_enable_bits(nb_dev, 0x48, 1 << 8, 0); |
| 343 | |
| 344 | set_nbmisc_enable_bits(nb_dev, 0x2A, 1 << 15 | 1 << 17, 1 << 17); |
| 345 | set_nbmisc_enable_bits(nb_dev, 0x2B, 1 << 15 | 1 << 27, 1 << 15 | 1 << 27); |
| 346 | set_nbmisc_enable_bits(nb_dev, 0x2C, 1 << 0 | 1 << 1 | 1 << 5 | 1 << 4 | 1 << 10, 1 << 0 | 1 << 1 | 1 << 5); |
| 347 | set_nbmisc_enable_bits(nb_dev, 0x32, 0x3F << 20, 0x2A << 20); |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 348 | set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 7 | 1 << 15 | 1 << 23, 0); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 349 | set_nbmisc_enable_bits(nb_dev, 0x35, 0x3F << 26, 0x2A << 26); |
| 350 | set_nbmisc_enable_bits(nb_dev, 0x37, 0xfff << 20, 0xddd << 20); |
| 351 | set_nbmisc_enable_bits(nb_dev, 0x37, 7 << 11, 0); |
| 352 | /* PCIE CDR setting */ |
| 353 | set_nbmisc_enable_bits(nb_dev, 0x38, 0xFFFFFFFF, 0xC0C0C0); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 354 | set_nbmisc_enable_bits(nb_dev, 0x22, 0xFFFFFFFF, (1 << 27) | (0x8 << 12) | (0x8 << 16) | (0x8 << 20)); |
| 355 | set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 1 | 1 << 2 | 1 << 6 | 1 << 7, 1 << 1 | 1 << 2 | 1 << 6 | 1 << 7); |
| 356 | |
| 357 | set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 4 | 1 << 24, 0xF << 4 | 1 << 24); |
| 358 | set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 10 | 1 << 11 | 1 << 26, 1 << 11); |
| 359 | set_nbmisc_enable_bits(nb_dev, 0x67, 3 << 21, 3 << 21); |
| 360 | set_nbmisc_enable_bits(nb_dev, 0x68, 1 << 8 | 1 << 9 | 1 << 19, 1 << 9 | 1 << 19); |
| 361 | set_nbmisc_enable_bits(nb_dev, 0x6B, 3 << 3 | 1 << 15 | 0x1F << 27, 3 << 3 | 1 << 15 | 0x1F << 27); |
| 362 | set_nbmisc_enable_bits(nb_dev, 0x6C, 0xFFFFFFFF, 0x41183000); |
| 363 | |
| 364 | /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL |
| 365 | * Block non-snoop DMA request if PMArbDis is set. |
| 366 | * Set BMSetDis */ |
| 367 | set_nbmisc_enable_bits(nb_dev, 0x0B, 0xFFFFFFFF, 0x00400180); |
| 368 | set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x00000310); |
| 369 | |
| 370 | /* NBCFG (NBMISCIND 0x0): NB_CNTL - |
| 371 | * HIDE_NB_AGP_CAP ([0], default=1)HIDE |
| 372 | * HIDE_P2P_AGP_CAP ([1], default=1)HIDE |
| 373 | * HIDE_NB_GART_BAR ([2], default=1)HIDE |
| 374 | * AGPMODE30 ([4], default=0)DISABLE |
| 375 | * AGP30ENCHANCED ([5], default=0)DISABLE |
| 376 | * HIDE_AGP_CAP ([8], default=1)ENABLE */ |
| 377 | set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 6); |
| 378 | |
| 379 | /* IOC_LAT_PERF_CNTR_CNTL */ |
| 380 | set_nbmisc_enable_bits(nb_dev, 0x30, 0xFF, 0x00); |
| 381 | //set_nbmisc_enable_bits(nb_dev, 0x31, 0xFF, 0x00); |
| 382 | |
| 383 | /* IOC_LAT_PERF_CNTR_OUT */ |
| 384 | /* IOC_JTAG_CNTL */ |
| 385 | set_nbmisc_enable_bits(nb_dev, 0x47, 0xFFFFFFFF, 0x0000000B); |
| 386 | |
| 387 | set_nbmisc_enable_bits(nb_dev, 0x12, 0xFFFFFFFF, 0x00FB5555); |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 388 | set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFFFFFFFF, 0x001F37FC); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 389 | set_nbmisc_enable_bits(nb_dev, 0x15, 0xFFFFFFFF, 0x0); |
| 390 | |
| 391 | /* NB_PROG_DEVICE_REMAP */ |
| 392 | set_nbmisc_enable_bits(nb_dev, 0x20, 0xFFFFFFFF, 0x0); |
| 393 | set_nbmisc_enable_bits(nb_dev, 0x21, 0xFFFFFFFF, 0x0); |
| 394 | |
| 395 | /* Compliant with CIM_33's MISC_INIT_TBL, except Hide NB_BAR3_PCIE |
| 396 | * Enable access to DEV8 |
| 397 | * Enable setPower message for all ports |
| 398 | */ |
| 399 | set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); |
| 400 | set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); |
| 401 | set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); |
| 402 | set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); |
| 403 | set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); |
| 404 | set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); |
| 405 | set_nbmisc_enable_bits(nb_dev, 0x5D, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); |
| 406 | set_nbmisc_enable_bits(nb_dev, 0x5F, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); |
| 407 | set_nbmisc_enable_bits(nb_dev, 0x61, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); |
| 408 | set_nbmisc_enable_bits(nb_dev, 0x63, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); |
| 409 | |
| 410 | /* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */ |
| 411 | set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x400180); |
| 412 | } |
| 413 | |
| 414 | /***************************************** |
| 415 | * Some setting is from rpr. Some is from CIMx. |
| 416 | *****************************************/ |
| 417 | static void sr5650_por_htiu_index_init(device_t nb_dev) |
| 418 | { |
| 419 | device_t cpu_f0; |
| 420 | |
| 421 | cpu_f0 = PCI_DEV(0, 0x18, 0); |
| 422 | |
| 423 | set_htiu_enable_bits(nb_dev, 0x1C, 0x1<<17, 0x1<<17); |
| 424 | set_htiu_enable_bits(nb_dev, 0x05, 0x1<<8, 0x1<<8); |
| 425 | set_htiu_enable_bits(nb_dev, 0x06, 0x1<<0, 0x0<<0); |
| 426 | set_htiu_enable_bits(nb_dev, 0x06, 0x1<<1, 0x1<<1); |
| 427 | set_htiu_enable_bits(nb_dev, 0x06, 0x1<<9, 0x1<<9); |
| 428 | set_htiu_enable_bits(nb_dev, 0x06, 0x1<<13, 0x1<<13); |
| 429 | set_htiu_enable_bits(nb_dev, 0x06, 0x1<<17, 0x1<<17); |
| 430 | set_htiu_enable_bits(nb_dev, 0x06, 0x3<<15, 0x3<<15); |
| 431 | set_htiu_enable_bits(nb_dev, 0x06, 0x1<<25, 0x1<<25); |
| 432 | set_htiu_enable_bits(nb_dev, 0x06, 0x1<<30, 0x1<<30); |
| 433 | |
| 434 | set_htiu_enable_bits(nb_dev, 0x07, 0x1 << 0 | 0x1 << 1 | 0x1 << 2, 0x1 << 0); |
| 435 | |
| 436 | set_htiu_enable_bits(nb_dev, 0x16, 0x1<<11, 0x1<<11); |
| 437 | |
| 438 | set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<2, 0x1<<2); |
| 439 | set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<4, 0x1<<4); |
| 440 | |
| 441 | set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 0 << 21); |
| 442 | axindxc_reg(0x10, 1 << 9, 1 << 9); |
| 443 | set_pcie_enable_bits(nb_dev, 0x10 | 5 << 16, 1 << 9, 1 << 9); |
| 444 | set_htiu_enable_bits(nb_dev, 0x06, 0x1<<26, 0x1<<26); |
| 445 | set_htiu_enable_bits(nb_dev, 0x16, 0x1<<10, 0x1<<10); |
| 446 | |
| 447 | /* Enable BIAS circuit for all lanes. */ |
| 448 | //set_htiu_enable_bits(nb_dev, 0x2B, 0xF<<28, 0xF<<28); |
| 449 | set_htiu_enable_bits(nb_dev, 0x2B, 0xF << 28, 0); |
| 450 | set_htiu_enable_bits(nb_dev, 0x05, 0xFFFFFF, 0xFF558); |
| 451 | set_htiu_enable_bits(nb_dev, 0x06, 0xFFFFFFFE, 0x04203A202); |
| 452 | set_htiu_enable_bits(nb_dev, 0x0C, 0xFFFF, 0x101); |
| 453 | |
| 454 | /* A21 only */ |
| 455 | //if (REV_SR5650_A21 == get_nb_rev(nb_dev)) { |
| 456 | if (get_nb_rev(nb_dev) > REV_SR5650_A11) { |
| 457 | set_htiu_enable_bits(nb_dev, 0x05, 0x3<<3| 1<<6 | 1<<10 | 0xFF<<12, 0x3<<3 | 1<<6 | 1<<10 | 0xFF<<12); |
| 458 | set_htiu_enable_bits(nb_dev, 0x1D, 1 << 2 | 1 << 4, 0); |
| 459 | } |
| 460 | } |
| 461 | |
| 462 | /***************************************** |
| 463 | * Compliant with CIM_33's ATINB_POR_INIT_JMPDI |
| 464 | * Configure SR5650 registers to power-on default RPR. |
| 465 | * POR: Power On Reset |
| 466 | * RPR: Register Programming Requirements |
| 467 | *****************************************/ |
| 468 | static void sr5650_por_init(device_t nb_dev) |
| 469 | { |
| 470 | printk(BIOS_INFO, "sr5650_por_init\n"); |
| 471 | /* ATINB_PCICFG_POR_TABLE, initialize the values for sr5650 PCI Config registers */ |
| 472 | sr5650_por_pcicfg_init(nb_dev); |
| 473 | |
| 474 | /* ATINB_MISCIND_POR_TABLE */ |
| 475 | sr5650_por_misc_index_init(nb_dev); |
| 476 | |
| 477 | /* ATINB_HTIUNBIND_POR_TABLE */ |
| 478 | sr5650_por_htiu_index_init(nb_dev); |
| 479 | |
| 480 | /* ATINB_CLKCFG_PORT_TABLE */ |
| 481 | /* sr5650 A11 SB Link full swing? */ |
| 482 | } |
| 483 | |
| 484 | /* enable CFG access to Dev8, which is the SB P2P Bridge */ |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 485 | void enable_sr5650_dev8(void) |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 486 | { |
| 487 | set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6); |
| 488 | } |
| 489 | |
| 490 | /* |
| 491 | * Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit). |
| 492 | */ |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 493 | void sr5650_before_pci_init(void) |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 494 | { |
| 495 | } |
| 496 | |
| 497 | /* |
| 498 | * The calling sequence is same as CIM. |
| 499 | */ |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 500 | void sr5650_early_setup(void) |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 501 | { |
| 502 | device_t nb_dev = PCI_DEV(0, 0, 0); |
| 503 | printk(BIOS_INFO, "sr5650_early_setup()\n"); |
| 504 | |
| 505 | /*ATINB_PrepareInit */ |
| 506 | get_cpu_rev(); |
| 507 | |
| 508 | switch (get_nb_rev(nb_dev)) { /* PCIEMiscInit */ |
| 509 | case REV_SR5650_A11: |
| 510 | printk(BIOS_INFO, "NB Revision is A11.\n"); |
| 511 | break; |
| 512 | case REV_SR5650_A12: |
| 513 | printk(BIOS_INFO, "NB Revision is A12.\n"); |
| 514 | break; |
| 515 | case REV_SR5650_A21: |
| 516 | printk(BIOS_INFO, "NB Revision is A21.\n"); |
| 517 | break; |
| 518 | } |
| 519 | |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 520 | fam10_optimization(); |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 521 | sr5650_por_init(nb_dev); |
| 522 | } |
| 523 | |
| 524 | /** |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 525 | * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 526 | * |
| 527 | */ |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 528 | void sr5650_disable_pcie_bridge(void) |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 529 | { |
| 530 | u32 mask; |
| 531 | u32 reg; |
| 532 | device_t nb_dev = PCI_DEV(0, 0, 0); |
| 533 | |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame^] | 534 | mask = (1 << 2) | (1 << 3); /*GPP1*/ |
| 535 | mask |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ |
| 536 | mask |= (1 << 18) | (1 << 19); /*GPP2*/ |
| 537 | mask |= (1 << 20); /*GPP3b*/ |
Zheng Bao | 98fcc09 | 2011-03-27 16:39:58 +0000 | [diff] [blame] | 538 | reg = mask; |
| 539 | set_nbmisc_enable_bits(nb_dev, 0x0c, mask, reg); |
| 540 | } |