commit af92d07503600695df44f59aa7c8f9c19b4e462d
author Eric Lai <eric_lai@quanta.corp-partner.google.com> Mon Mar 14 15:08:27 2022 +0800
committer Tim Wawrzynczak <twawrzynczak@chromium.org> Thu Mar 17 16:00:38 2022 +0000
tree a125ec51ee5f46c1ec7de8f9f3478ffddfc3c82c
parent 275478711009ffed866fbc0f30ff2130447913f4

mb/google/brya: Remove mainboard.asl

Use C code to generate MS0X entry and provide variant hook.

BUG=b:207144468
TEST=check SSDT table has the same entry.
    Scope (\_SB)
    {
        Method (MS0X, 1, Serialized)
        {
            If ((Arg0 == One))
            {
                \_SB.PCI0.CTXS (0x148)
            }
            Else
            {
                \_SB.PCI0.STXS (0x148)
            }
        }
    }

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/brya/mainboard.c

diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c
index 42536bb..b3f42ca 100644
--- a/src/mainboard/google/brya/mainboard.c
+++ b/src/mainboard/google/brya/mainboard.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <acpi/acpigen.h>
+#include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <device/device.h>
 #include <drivers/tpm/cr50.h>
@@ -109,6 +110,23 @@
 	}
 }
 
+static void mainboard_generate_s0ix_hook(void)
+{
+	acpigen_write_if_lequal_op_int(ARG0_OP, 1);
+	{
+		if (CONFIG(HAVE_SLP_S0_GATE))
+			acpigen_soc_clear_tx_gpio(GPIO_SLP_S0_GATE);
+		variant_generate_s0ix_hook(S0IX_ENTRY);
+	}
+	acpigen_write_else();
+	{
+		if (CONFIG(HAVE_SLP_S0_GATE))
+			acpigen_soc_set_tx_gpio(GPIO_SLP_S0_GATE);
+		variant_generate_s0ix_hook(S0IX_EXIT);
+	}
+	acpigen_write_if_end();
+}
+
 static void mainboard_fill_ssdt(const struct device *dev)
 {
 	const struct device *wwan = DEV_PTR(rp6_wwan);
@@ -122,6 +140,13 @@
 	}
 	/* for variant to fill additional SSDT */
 	variant_fill_ssdt(dev);
+
+	acpigen_write_scope("\\_SB");
+	acpigen_write_method_serialized("MS0X", 1);
+	mainboard_generate_s0ix_hook();
+	acpigen_write_method_end(); /* Method */
+	acpigen_write_scope_end(); /* Scope */
+
 }
 
 void __weak variant_fill_ssdt(const struct device *dev)
@@ -129,6 +154,19 @@
 	/* Add board-specific SSDT entries */
 }
 
+void __weak variant_generate_s0ix_hook(enum s0ix_entry)
+{
+	/* Add board-specific MS0X entries */
+	/*
+	   if (s0ix_entry == S0IX_ENTRY) {
+		implement variant operations here
+	   }
+	   if (s0ix_entry == S0IX_EXIT) {
+		implement variant operations here
+	   }
+	 */
+}
+
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_dev_init;