mb/google/brya: Remove mainboard.asl
Use C code to generate MS0X entry and provide variant hook.
BUG=b:207144468
TEST=check SSDT table has the same entry.
Scope (\_SB)
{
Method (MS0X, 1, Serialized)
{
If ((Arg0 == One))
{
\_SB.PCI0.CTXS (0x148)
}
Else
{
\_SB.PCI0.STXS (0x148)
}
}
}
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl
index fed071b..82cafcf 100644
--- a/src/mainboard/google/brya/dsdt.asl
+++ b/src/mainboard/google/brya/dsdt.asl
@@ -22,7 +22,6 @@
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
- #include "mainboard.asl"
#if CONFIG(HAVE_WWAN_POWER_SEQUENCE)
#include "wwan_power.asl"
#endif
diff --git a/src/mainboard/google/brya/mainboard.asl b/src/mainboard/google/brya/mainboard.asl
deleted file mode 100644
index 8ca694d..0000000
--- a/src/mainboard/google/brya/mainboard.asl
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-
-#if CONFIG(HAVE_SLP_S0_GATE)
-/*
- * S0ix Entry/Exit Notifications
- * Called from \_SB.PEPD._DSM
- */
-Method (MS0X, 1, Serialized)
-{
- If (Arg0 == 1) {
- /*
- * On S0ix entry, clear the SLP_S0_GATE pin, so that the rest of
- * the platform can transition to its low power state as well.
- */
- \_SB.PCI0.CTXS(GPIO_SLP_S0_GATE);
- } Else {
- /*
- * On S0ix exit, set the SLP_S0_GATE pin, so that the rest of
- * the platform will resume from its low power state.
- */
- \_SB.PCI0.STXS(GPIO_SLP_S0_GATE);
- }
-}
-#endif
diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c
index 42536bb..b3f42ca 100644
--- a/src/mainboard/google/brya/mainboard.c
+++ b/src/mainboard/google/brya/mainboard.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpigen.h>
+#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <device/device.h>
#include <drivers/tpm/cr50.h>
@@ -109,6 +110,23 @@
}
}
+static void mainboard_generate_s0ix_hook(void)
+{
+ acpigen_write_if_lequal_op_int(ARG0_OP, 1);
+ {
+ if (CONFIG(HAVE_SLP_S0_GATE))
+ acpigen_soc_clear_tx_gpio(GPIO_SLP_S0_GATE);
+ variant_generate_s0ix_hook(S0IX_ENTRY);
+ }
+ acpigen_write_else();
+ {
+ if (CONFIG(HAVE_SLP_S0_GATE))
+ acpigen_soc_set_tx_gpio(GPIO_SLP_S0_GATE);
+ variant_generate_s0ix_hook(S0IX_EXIT);
+ }
+ acpigen_write_if_end();
+}
+
static void mainboard_fill_ssdt(const struct device *dev)
{
const struct device *wwan = DEV_PTR(rp6_wwan);
@@ -122,6 +140,13 @@
}
/* for variant to fill additional SSDT */
variant_fill_ssdt(dev);
+
+ acpigen_write_scope("\\_SB");
+ acpigen_write_method_serialized("MS0X", 1);
+ mainboard_generate_s0ix_hook();
+ acpigen_write_method_end(); /* Method */
+ acpigen_write_scope_end(); /* Scope */
+
}
void __weak variant_fill_ssdt(const struct device *dev)
@@ -129,6 +154,19 @@
/* Add board-specific SSDT entries */
}
+void __weak variant_generate_s0ix_hook(enum s0ix_entry)
+{
+ /* Add board-specific MS0X entries */
+ /*
+ if (s0ix_entry == S0IX_ENTRY) {
+ implement variant operations here
+ }
+ if (s0ix_entry == S0IX_EXIT) {
+ implement variant operations here
+ }
+ */
+}
+
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_dev_init;
diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
index 7c1ce21..9accc08 100644
--- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
@@ -25,6 +25,13 @@
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config);
void variant_fill_ssdt(const struct device *dev);
+enum s0ix_entry {
+ S0IX_EXIT,
+ S0IX_ENTRY,
+};
+
+void variant_generate_s0ix_hook(enum s0ix_entry);
+
/* Modify devictree settings during ramstage */
void variant_devtree_update(void);
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
index 068aaa4..51e4b20 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h
@@ -16,5 +16,7 @@
#define GPIO_EC_IN_RW GPP_F18
/* GPIO IRQ for tight timestamps */
#define EC_SYNC_IRQ GPD2_IRQ
+/* GPP_H18 used as dummy here since nissa not selected HAVE_SLP_S0_GATE */
+#define GPIO_SLP_S0_GATE GPP_H18
#endif /* __BASEBOARD_GPIO_H__ */