| /** @file |
| |
| Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> |
| |
| Redistribution and use in source and binary forms, with or without modification, |
| are permitted provided that the following conditions are met: |
| |
| * Redistributions of source code must retain the above copyright notice, this |
| list of conditions and the following disclaimer. |
| * Redistributions in binary form must reproduce the above copyright notice, this |
| list of conditions and the following disclaimer in the documentation and/or |
| other materials provided with the distribution. |
| * Neither the name of Intel Corporation nor the names of its contributors may |
| be used to endorse or promote products derived from this software without |
| specific prior written permission. |
| |
| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| THE POSSIBILITY OF SUCH DAMAGE. |
| |
| This file is automatically generated. Please do NOT modify !!! |
| |
| **/ |
| |
| #ifndef __FSPMUPD_H__ |
| #define __FSPMUPD_H__ |
| |
| #include <FspUpd.h> |
| |
| #pragma pack(1) |
| |
| |
| #include <MemInfoHob.h> |
| |
| /// |
| /// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. |
| /// |
| typedef struct { |
| UINT8 Revision; ///< Chipset Init Info Revision |
| UINT8 Rsvd[3]; ///< Reserved |
| UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table |
| UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table |
| } CHIPSET_INIT_INFO; |
| |
| |
| /** Fsp M Configuration |
| **/ |
| typedef struct { |
| |
| /** Offset 0x0040 - Platform Reserved Memory Size |
| The minimum platform memory size required to pass control into DXE |
| **/ |
| UINT64 PlatformMemorySize; |
| |
| /** Offset 0x0048 - SPD Data Length |
| Length of SPD Data |
| 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes |
| **/ |
| UINT16 MemorySpdDataLen; |
| |
| /** Offset 0x004A - Reserved |
| **/ |
| UINT8 Reserved0; |
| |
| /** Offset 0x004B - Enable/Disable CrashLog Device 10 |
| Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog |
| $EN_DIS |
| **/ |
| UINT8 CpuCrashLogDevice; |
| |
| /** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr000; |
| |
| /** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr001; |
| |
| /** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr010; |
| |
| /** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr011; |
| |
| /** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr020; |
| |
| /** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr021; |
| |
| /** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr030; |
| |
| /** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr031; |
| |
| /** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr100; |
| |
| /** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr101; |
| |
| /** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr110; |
| |
| /** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr111; |
| |
| /** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr120; |
| |
| /** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr121; |
| |
| /** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr130; |
| |
| /** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 |
| Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| **/ |
| UINT32 MemorySpdPtr131; |
| |
| /** Offset 0x008C - RcompResistor settings |
| Indicates RcompResistor settings: Board-dependent |
| **/ |
| UINT16 RcompResistor; |
| |
| /** Offset 0x008E - RcompTarget settings |
| RcompTarget settings: board-dependent |
| **/ |
| UINT16 RcompTarget[5]; |
| |
| /** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc0Ch0[2]; |
| |
| /** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc0Ch1[2]; |
| |
| /** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc0Ch2[2]; |
| |
| /** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc0Ch3[2]; |
| |
| /** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc1Ch0[2]; |
| |
| /** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc1Ch1[2]; |
| |
| /** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc1Ch2[2]; |
| |
| /** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3 |
| Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| **/ |
| UINT8 DqsMapCpu2DramMc1Ch3[2]; |
| |
| /** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0 |
| Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc0Ch0[16]; |
| |
| /** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1 |
| Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc0Ch1[16]; |
| |
| /** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2 |
| Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc0Ch2[16]; |
| |
| /** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3 |
| Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc0Ch3[16]; |
| |
| /** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0 |
| Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc1Ch0[16]; |
| |
| /** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1 |
| Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc1Ch1[16]; |
| |
| /** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2 |
| Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc1Ch2[16]; |
| |
| /** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3 |
| Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| **/ |
| UINT8 DqMapCpu2DramMc1Ch3[16]; |
| |
| /** Offset 0x0128 - Dqs Pins Interleaved Setting |
| Indicates DqPinsInterleaved setting: board-dependent |
| $EN_DIS |
| **/ |
| UINT8 DqPinsInterleaved; |
| |
| /** Offset 0x0129 - Reserved |
| **/ |
| UINT8 Reserved1[7]; |
| |
| /** Offset 0x0130 - Tseg Size |
| Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build |
| 0x0400000:4MB, 0x01000000:16MB |
| **/ |
| UINT32 TsegSize; |
| |
| /** Offset 0x0134 - Reserved |
| **/ |
| UINT8 Reserved2[3]; |
| |
| /** Offset 0x0137 - Enable SMBus |
| Enable/disable SMBus controller. |
| $EN_DIS |
| **/ |
| UINT8 SmbusEnable; |
| |
| /** Offset 0x0138 - Spd Address Tabl |
| Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used |
| if SPD Address is 00 |
| **/ |
| UINT8 SpdAddressTable[16]; |
| |
| /** Offset 0x0148 - Platform Debug Consent |
| Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks |
| s0ix\n |
| \n |
| Enabled(Low Power) does not support DCI OOB 4-wire and Tracehub is powergated by |
| default, s0ix is viable\n |
| \n |
| Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users |
| 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual |
| **/ |
| UINT8 PlatformDebugConsent; |
| |
| /** Offset 0x0149 - Reserved |
| **/ |
| UINT8 Reserved3[21]; |
| |
| /** Offset 0x015E - State of X2APIC_OPT_OUT bit in the DMAR table |
| 0=Disable/Clear, 1=Enable/Set |
| $EN_DIS |
| **/ |
| UINT8 X2ApicOptOut; |
| |
| /** Offset 0x015F - Reserved |
| **/ |
| UINT8 Reserved4; |
| |
| /** Offset 0x0160 - Base addresses for VT-d function MMIO access |
| Base addresses for VT-d MMIO access per VT-d engine |
| **/ |
| UINT32 VtdBaseAddress[9]; |
| |
| /** Offset 0x0184 - Disable VT-d |
| 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) |
| $EN_DIS |
| **/ |
| UINT8 VtdDisable; |
| |
| /** Offset 0x0185 - Reserved |
| **/ |
| UINT8 Reserved5[2]; |
| |
| /** Offset 0x0187 - Internal Graphics Pre-allocated Memory |
| Size of memory preallocated for internal graphics. |
| 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, |
| 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, |
| 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB |
| **/ |
| UINT8 IgdDvmt50PreAlloc; |
| |
| /** Offset 0x0188 - Internal Graphics |
| Enable/disable internal graphics. |
| $EN_DIS |
| **/ |
| UINT8 InternalGfx; |
| |
| /** Offset 0x0189 - Board Type |
| MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile |
| Halo, 7=UP Server |
| 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server |
| **/ |
| UINT8 UserBd; |
| |
| /** Offset 0x018A - Reserved |
| **/ |
| UINT8 Reserved6[2]; |
| |
| /** Offset 0x018C - DDR Frequency Limit |
| Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, |
| 2133, 2400, 2667, 2933 and 0 for Auto. |
| 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto |
| **/ |
| UINT16 DdrFreqLimit; |
| |
| /** Offset 0x018E - SAGV |
| System Agent dynamic frequency support. |
| 0:Disabled, 1:Enabled |
| **/ |
| UINT8 SaGv; |
| |
| /** Offset 0x018F - Reserved |
| **/ |
| UINT8 Reserved7[3]; |
| |
| /** Offset 0x0192 - Controller 0 Channel 0 DIMM Control |
| Enable / Disable DIMMs on Controller 0 Channel 0 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc0Ch0; |
| |
| /** Offset 0x0193 - Controller 0 Channel 1 DIMM Control |
| Enable / Disable DIMMs on Controller 0 Channel 1 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc0Ch1; |
| |
| /** Offset 0x0194 - Controller 0 Channel 2 DIMM Control |
| Enable / Disable DIMMs on Controller 0 Channel 2 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc0Ch2; |
| |
| /** Offset 0x0195 - Controller 0 Channel 3 DIMM Control |
| Enable / Disable DIMMs on Controller 0 Channel 3 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc0Ch3; |
| |
| /** Offset 0x0196 - Controller 1 Channel 0 DIMM Control |
| Enable / Disable DIMMs on Controller 1 Channel 0 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc1Ch0; |
| |
| /** Offset 0x0197 - Controller 1 Channel 1 DIMM Control |
| Enable / Disable DIMMs on Controller 1 Channel 1 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc1Ch1; |
| |
| /** Offset 0x0198 - Controller 1 Channel 2 DIMM Control |
| Enable / Disable DIMMs on Controller 1 Channel 2 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc1Ch2; |
| |
| /** Offset 0x0199 - Controller 1 Channel 3 DIMM Control |
| Enable / Disable DIMMs on Controller 1 Channel 3 |
| $EN_DIS |
| **/ |
| UINT8 DisableMc1Ch3; |
| |
| /** Offset 0x019A - Reserved |
| **/ |
| UINT8 Reserved8[4]; |
| |
| /** Offset 0x019E - Memory Reference Clock |
| 100MHz, 133MHz. |
| 0:133MHz, 1:100MHz |
| **/ |
| UINT8 RefClk; |
| |
| /** Offset 0x019F - Reserved |
| **/ |
| UINT8 Reserved9[37]; |
| |
| /** Offset 0x01C4 - Enable Intel HD Audio (Azalia) |
| 0: Disable, 1: Enable (Default) Azalia controller |
| $EN_DIS |
| **/ |
| UINT8 PchHdaEnable; |
| |
| /** Offset 0x01C5 - Enable PCH ISH Controller |
| 0: Disable, 1: Enable (Default) ISH Controller |
| $EN_DIS |
| **/ |
| UINT8 PchIshEnable; |
| |
| /** Offset 0x01C6 - Reserved |
| **/ |
| UINT8 Reserved10[45]; |
| |
| /** Offset 0x01F3 - Enable/Disable SA IPU |
| Enable(Default): Enable SA IPU, Disable: Disable SA IPU |
| $EN_DIS |
| **/ |
| UINT8 SaIpuEnable; |
| |
| /** Offset 0x01F4 - IMGU CLKOUT Configuration |
| The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>. |
| $EN_DIS |
| **/ |
| UINT8 ImguClkOutEn[6]; |
| |
| /** Offset 0x01FA - Program GPIOs for LFP on DDI port-A device |
| 0=Disabled,1(Default)=eDP, 2=MIPI DSI |
| 0:Disabled, 1:eDP, 2:MIPI DSI |
| **/ |
| UINT8 DdiPortAConfig; |
| |
| /** Offset 0x01FB - Program GPIOs for LFP on DDI port-B device |
| 0(Default)=Disabled,1=eDP, 2=MIPI DSI |
| 0:Disabled, 1:eDP, 2:MIPI DSI |
| **/ |
| UINT8 DdiPortBConfig; |
| |
| /** Offset 0x01FC - Enable or disable HPD of DDI port A |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPortAHpd; |
| |
| /** Offset 0x01FD - Enable or disable HPD of DDI port B |
| 0=Disable, 1(Default)=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPortBHpd; |
| |
| /** Offset 0x01FE - Enable or disable HPD of DDI port C |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPortCHpd; |
| |
| /** Offset 0x01FF - Enable or disable HPD of DDI port 1 |
| 0=Disable, 1(Default)=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort1Hpd; |
| |
| /** Offset 0x0200 - Enable or disable HPD of DDI port 2 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort2Hpd; |
| |
| /** Offset 0x0201 - Enable or disable HPD of DDI port 3 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort3Hpd; |
| |
| /** Offset 0x0202 - Enable or disable HPD of DDI port 4 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort4Hpd; |
| |
| /** Offset 0x0203 - Enable or disable DDC of DDI port A |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPortADdc; |
| |
| /** Offset 0x0204 - Enable or disable DDC of DDI port B |
| 0=Disable, 1(Default)=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPortBDdc; |
| |
| /** Offset 0x0205 - Enable or disable DDC of DDI port C |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPortCDdc; |
| |
| /** Offset 0x0206 - Enable DDC setting of DDI Port 1 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort1Ddc; |
| |
| /** Offset 0x0207 - Enable DDC setting of DDI Port 2 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort2Ddc; |
| |
| /** Offset 0x0208 - Enable DDC setting of DDI Port 3 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort3Ddc; |
| |
| /** Offset 0x0209 - Enable DDC setting of DDI Port 4 |
| 0(Default)=Disable, 1=Enable |
| $EN_DIS |
| **/ |
| UINT8 DdiPort4Ddc; |
| |
| /** Offset 0x020A - Reserved |
| **/ |
| UINT8 Reserved11[136]; |
| |
| /** Offset 0x0292 - DMI Gen3 Root port preset values per lane |
| Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane |
| **/ |
| UINT8 DmiGen3RootPortPreset[8]; |
| |
| /** Offset 0x029A - Reserved |
| **/ |
| UINT8 Reserved12[189]; |
| |
| /** Offset 0x0357 - Hyper Threading Enable/Disable |
| Enable or Disable Hyper-Threading Technology. 0: Disable; <b>1: Enable</b> |
| $EN_DIS |
| **/ |
| UINT8 HyperThreading; |
| |
| /** Offset 0x0358 - Reserved |
| **/ |
| UINT8 Reserved13; |
| |
| /** Offset 0x0359 - CPU ratio value |
| This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio |
| set by Hardware (HFM). Valid Range 0 to 63. |
| **/ |
| UINT8 CpuRatio; |
| |
| /** Offset 0x035A - Reserved |
| **/ |
| UINT8 Reserved14[2]; |
| |
| /** Offset 0x035C - Processor Early Power On Configuration FCLK setting |
| FCLK frequency can take values of 400MHz, 800MHz and 1GHz. <b>0: 800 MHz (ULT/ULX)</b>. |
| <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved |
| 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved |
| **/ |
| UINT8 FClkFrequency; |
| |
| /** Offset 0x035D - Enable or Disable VMX |
| Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities |
| provided by Vanderpool Technology. 0: Disable; <b>1: Enable</b>. |
| $EN_DIS |
| **/ |
| UINT8 VmxEnable; |
| |
| /** Offset 0x035E - Reserved |
| **/ |
| UINT8 Reserved15[20]; |
| |
| /** Offset 0x0372 - Enable or Disable TME |
| Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks. |
| <b>0: Disable</b>; 1: Enable. |
| $EN_DIS |
| **/ |
| UINT8 TmeEnable; |
| |
| /** Offset 0x0373 - Enable CPU CrashLog |
| Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>. |
| $EN_DIS |
| **/ |
| UINT8 CpuCrashLogEnable; |
| |
| /** Offset 0x0374 - Reserved |
| **/ |
| UINT8 Reserved16[254]; |
| |
| /** Offset 0x0472 - GPIO Override |
| Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings |
| before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO |
| configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use |
| **/ |
| UINT8 GpioOverride; |
| |
| /** Offset 0x0473 - Reserved |
| **/ |
| UINT8 Reserved17[240]; |
| |
| /** Offset 0x0563 - Thermal Design Current enable/disable |
| Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA, |
| [1] for GT, [2] for SA, [3] and [4] are Reserved. |
| **/ |
| UINT8 TdcEnable[5]; |
| |
| /** Offset 0x0568 - Thermal Design Current time window |
| TDC Time Window, value of IA either in milliseconds or seconds, value of GT/SA is |
| in milliseconds. 1ms is default. Range of IA from 1ms to 448s, Range of GT/SA is |
| 1ms to 10ms, except for 9ms. 9ms has no valid encoding in the MSR definition. |
| **/ |
| UINT32 TdcTimeWindow[5]; |
| |
| /** Offset 0x057C - Reserved |
| **/ |
| UINT8 Reserved18[156]; |
| |
| /** Offset 0x0618 - BiosGuard |
| Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable |
| $EN_DIS |
| **/ |
| UINT8 BiosGuard; |
| |
| /** Offset 0x0619 |
| **/ |
| UINT8 BiosGuardToolsInterface; |
| |
| /** Offset 0x061A - Reserved |
| **/ |
| UINT8 Reserved19[2]; |
| |
| /** Offset 0x061C - PrmrrSize |
| Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable |
| **/ |
| UINT32 PrmrrSize; |
| |
| /** Offset 0x0620 - SinitMemorySize |
| Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable |
| **/ |
| UINT32 SinitMemorySize; |
| |
| /** Offset 0x0624 - Reserved |
| **/ |
| UINT8 Reserved20[12]; |
| |
| /** Offset 0x0630 - TxtHeapMemorySize |
| Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable |
| **/ |
| UINT32 TxtHeapMemorySize; |
| |
| /** Offset 0x0634 - TxtDprMemorySize |
| Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize |
| , 1: enable |
| **/ |
| UINT32 TxtDprMemorySize; |
| |
| /** Offset 0x0638 - Reserved |
| **/ |
| UINT8 Reserved21[604]; |
| |
| /** Offset 0x0894 - Number of RsvdSmbusAddressTable. |
| The number of elements in the RsvdSmbusAddressTable. |
| **/ |
| UINT8 PchNumRsvdSmbusAddresses; |
| |
| /** Offset 0x0895 - Reserved |
| **/ |
| UINT8 Reserved22[4]; |
| |
| /** Offset 0x0899 - Usage type for ClkSrc |
| 0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used |
| **/ |
| UINT8 PcieClkSrcUsage[18]; |
| |
| /** Offset 0x08AB - Reserved |
| **/ |
| UINT8 Reserved23[14]; |
| |
| /** Offset 0x08B9 - ClkReq-to-ClkSrc mapping |
| Number of ClkReq signal assigned to ClkSrc |
| **/ |
| UINT8 PcieClkSrcClkReq[18]; |
| |
| /** Offset 0x08CB - Reserved |
| **/ |
| UINT8 Reserved24[53]; |
| |
| /** Offset 0x0900 - Enable PCIE RP Mask |
| Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 |
| for port1, bit1 for port2, and so on. |
| **/ |
| UINT32 PcieRpEnableMask; |
| |
| /** Offset 0x0904 - Reserved |
| **/ |
| UINT8 Reserved25[2]; |
| |
| /** Offset 0x0906 - Enable HD Audio Link |
| Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. |
| $EN_DIS |
| **/ |
| UINT8 PchHdaAudioLinkHdaEnable; |
| |
| /** Offset 0x0907 - Reserved |
| **/ |
| UINT8 Reserved26[3]; |
| |
| /** Offset 0x090A - Enable HD Audio DMIC_N Link |
| Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. |
| **/ |
| UINT8 PchHdaAudioLinkDmicEnable[2]; |
| |
| /** Offset 0x090C - DMIC<N> ClkA Pin Muxing (N - DMIC number) |
| Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* |
| **/ |
| UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; |
| |
| /** Offset 0x0914 - DMIC<N> ClkB Pin Muxing |
| Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_* |
| **/ |
| UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; |
| |
| /** Offset 0x091C - Enable HD Audio DSP |
| Enable/disable HD Audio DSP feature. |
| $EN_DIS |
| **/ |
| UINT8 PchHdaDspEnable; |
| |
| /** Offset 0x091D - Reserved |
| **/ |
| UINT8 Reserved27[3]; |
| |
| /** Offset 0x0920 - DMIC<N> Data Pin Muxing |
| Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* |
| **/ |
| UINT32 PchHdaAudioLinkDmicDataPinMux[2]; |
| |
| /** Offset 0x0928 - Enable HD Audio SSP0 Link |
| Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 |
| **/ |
| UINT8 PchHdaAudioLinkSspEnable[6]; |
| |
| /** Offset 0x092E - Enable HD Audio SoundWire#N Link |
| Enable/disable HD Audio SNDW#N link. Muxed with HDA. |
| **/ |
| UINT8 PchHdaAudioLinkSndwEnable[4]; |
| |
| /** Offset 0x0932 - iDisp-Link Frequency |
| iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. |
| 4: 96MHz, 3: 48MHz |
| **/ |
| UINT8 PchHdaIDispLinkFrequency; |
| |
| /** Offset 0x0933 - iDisp-Link T-mode |
| iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T |
| 0: 2T, 2: 4T, 3: 8T, 4: 16T |
| **/ |
| UINT8 PchHdaIDispLinkTmode; |
| |
| /** Offset 0x0934 - iDisplay Audio Codec disconnection |
| 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. |
| $EN_DIS |
| **/ |
| UINT8 PchHdaIDispCodecDisconnect; |
| |
| /** Offset 0x0935 - Reserved |
| **/ |
| UINT8 Reserved28[7]; |
| |
| /** Offset 0x093C - CNVi DDR RFI Mitigation |
| Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE |
| $EN_DIS |
| **/ |
| UINT8 CnviDdrRfim; |
| |
| /** Offset 0x093D - Reserved |
| **/ |
| UINT8 Reserved29[11]; |
| |
| /** Offset 0x0948 - Debug Interfaces |
| Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, |
| BIT2 - Not used. |
| **/ |
| UINT8 PcdDebugInterfaceFlags; |
| |
| /** Offset 0x0949 - Serial Io Uart Debug Controller Number |
| Select SerialIo Uart Controller for debug. |
| 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 |
| **/ |
| UINT8 SerialIoUartDebugControllerNumber; |
| |
| /** Offset 0x094A - Reserved |
| **/ |
| UINT8 Reserved30[14]; |
| |
| /** Offset 0x0958 - ISA Serial Base selection |
| Select ISA Serial Base address. Default is 0x3F8. |
| 0:0x3F8, 1:0x2F8 |
| **/ |
| UINT8 PcdIsaSerialUartBase; |
| |
| /** Offset 0x0959 - Reserved |
| **/ |
| UINT8 Reserved31[4]; |
| |
| /** Offset 0x095D - TCSS Thunderbolt PCIE Root Port 0 Enable |
| Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssItbtPcie0En; |
| |
| /** Offset 0x095E - TCSS Thunderbolt PCIE Root Port 1 Enable |
| Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssItbtPcie1En; |
| |
| /** Offset 0x095F - TCSS Thunderbolt PCIE Root Port 2 Enable |
| Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssItbtPcie2En; |
| |
| /** Offset 0x0960 - TCSS Thunderbolt PCIE Root Port 3 Enable |
| Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssItbtPcie3En; |
| |
| /** Offset 0x0961 - TCSS USB HOST (xHCI) Enable |
| Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below |
| $EN_DIS |
| **/ |
| UINT8 TcssXhciEn; |
| |
| /** Offset 0x0962 - TCSS USB DEVICE (xDCI) Enable |
| Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssXdciEn; |
| |
| /** Offset 0x0963 - TCSS DMA0 Enable |
| Set TCSS DMA0. 0:Disabled 1:Enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssDma0En; |
| |
| /** Offset 0x0964 - TCSS DMA1 Enable |
| Set TCSS DMA1. 0:Disabled 1:Enabled |
| $EN_DIS |
| **/ |
| UINT8 TcssDma1En; |
| |
| /** Offset 0x0965 - Reserved |
| **/ |
| UINT8 Reserved32[2]; |
| |
| /** Offset 0x0967 - Early Command Training |
| Enables/Disable Early Command Training |
| $EN_DIS |
| **/ |
| UINT8 ECT; |
| |
| /** Offset 0x0968 - Reserved |
| **/ |
| UINT8 Reserved33[22]; |
| |
| /** Offset 0x097E - Late Command Training |
| Enables/Disable Late Command Training |
| $EN_DIS |
| **/ |
| UINT8 LCT; |
| |
| /** Offset 0x097F - Reserved |
| **/ |
| UINT8 Reserved34; |
| |
| /** Offset 0x0980 - Rank Margin Tool |
| Enable/disable Rank Margin Tool |
| $EN_DIS |
| **/ |
| UINT8 RMT; |
| |
| /** Offset 0x0981 - Reserved |
| **/ |
| UINT8 Reserved35[41]; |
| |
| /** Offset 0x09AA - IbeccParity |
| In-Band ECC Parity Control |
| $EN_DIS |
| **/ |
| UINT8 IbeccParity; |
| |
| /** Offset 0x09AB - IbeccOperationMode |
| In-Band ECC Operation Mode |
| 0:Protect base on address range, 1: Non-protected, 2: All protected |
| **/ |
| UINT8 IbeccOperationMode; |
| |
| /** Offset 0x09AC - IbeccProtectedRegionEnable |
| In-Band ECC Protected Region Enable |
| $EN_DIS |
| **/ |
| UINT8 IbeccProtectedRegionEnable[8]; |
| |
| /** Offset 0x09B4 - IbeccProtectedRegionBases |
| IBECC Protected Region Bases per IBECC instance |
| **/ |
| UINT16 IbeccProtectedRegionBase[8]; |
| |
| /** Offset 0x09C4 - IbeccProtectedRegionMasks |
| IBECC Protected Region Masks |
| **/ |
| UINT16 IbeccProtectedRegionMask[8]; |
| |
| /** Offset 0x09D4 - IbeccProtectedRegionOverallBases |
| IBECC Protected Region Bases based on enabled IBECC instance |
| **/ |
| UINT16 IbeccProtectedRegionOverallBase[8]; |
| |
| /** Offset 0x09E4 - Reserved |
| **/ |
| UINT8 Reserved36[18]; |
| |
| /** Offset 0x09F6 - Ch Hash Mask |
| Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to |
| BITS [19:6] Default is 0x30CC |
| **/ |
| UINT16 ChHashMask; |
| |
| /** Offset 0x09F8 - Reserved |
| **/ |
| UINT8 Reserved37[65]; |
| |
| /** Offset 0x0A39 - PcdSerialDebugLevel |
| Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, |
| Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, |
| Info & Verbose. |
| 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load |
| Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose |
| **/ |
| UINT8 PcdSerialDebugLevel; |
| |
| /** Offset 0x0A3A - Reserved |
| **/ |
| UINT8 Reserved38[8]; |
| |
| /** Offset 0x0A42 - TCSS USB Port Enable |
| Bitmap for per port enabling |
| **/ |
| UINT8 UsbTcPortEnPreMem; |
| |
| /** Offset 0x0A43 - Reserved |
| **/ |
| UINT8 Reserved39[26]; |
| |
| /** Offset 0x0A5D - SerialDebugMrcLevel |
| MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, |
| Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, |
| Info & Verbose. |
| 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load |
| Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose |
| **/ |
| UINT8 SerialDebugMrcLevel; |
| |
| /** Offset 0x0A5E - Reserved |
| **/ |
| UINT8 Reserved40[17]; |
| |
| /** Offset 0x0A6F - Skip external display device scanning |
| Enable: Do not scan for external display device, Disable (Default): Scan external |
| display devices |
| $EN_DIS |
| **/ |
| UINT8 SkipExtGfxScan; |
| |
| /** Offset 0x0A70 - Reserved |
| **/ |
| UINT8 Reserved41; |
| |
| /** Offset 0x0A71 - Lock PCU Thermal Management registers |
| Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 |
| $EN_DIS |
| **/ |
| UINT8 LockPTMregs; |
| |
| /** Offset 0x0A72 - Reserved |
| **/ |
| UINT8 Reserved42[118]; |
| |
| /** Offset 0x0AE8 - Smbus dynamic power gating |
| Disable or Enable Smbus dynamic power gating. |
| $EN_DIS |
| **/ |
| UINT8 SmbusDynamicPowerGating; |
| |
| /** Offset 0x0AE9 - Disable and Lock Watch Dog Register |
| Set 1 to clear WDT status, then disable and lock WDT registers. |
| $EN_DIS |
| **/ |
| UINT8 WdtDisableAndLock; |
| |
| /** Offset 0x0AEA - Reserved |
| **/ |
| UINT8 Reserved43[8]; |
| |
| /** Offset 0x0AF2 - Skip CPU replacement check |
| Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check |
| $EN_DIS |
| **/ |
| UINT8 SkipCpuReplacementCheck; |
| |
| /** Offset 0x0AF3 - Reserved |
| **/ |
| UINT8 Reserved44[2]; |
| |
| /** Offset 0x0AF5 - Serial Io Uart Debug Mode |
| Select SerialIo Uart Controller mode |
| 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, |
| 4:SerialIoUartSkipInit |
| **/ |
| UINT8 SerialIoUartDebugMode; |
| |
| /** Offset 0x0AF6 - Reserved |
| **/ |
| UINT8 Reserved45[42]; |
| } FSP_M_CONFIG; |
| |
| /** Fsp M UPD Configuration |
| **/ |
| typedef struct { |
| |
| /** Offset 0x0000 |
| **/ |
| FSP_UPD_HEADER FspUpdHeader; |
| |
| /** Offset 0x0020 |
| **/ |
| FSPM_ARCH_UPD FspmArchUpd; |
| |
| /** Offset 0x0040 |
| **/ |
| FSP_M_CONFIG FspmConfig; |
| |
| /** Offset 0x0B20 |
| **/ |
| UINT8 UnusedUpdSpace37[6]; |
| |
| /** Offset 0x0B26 |
| **/ |
| UINT16 UpdTerminator; |
| } FSPM_UPD; |
| |
| #pragma pack() |
| |
| #endif |