Rename ECAM-specific MMCONF Kconfigs
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig
index 27c9c21..941972b 100644
--- a/src/northbridge/amd/agesa/family14/Kconfig
+++ b/src/northbridge/amd/agesa/family14/Kconfig
@@ -11,10 +11,10 @@
hex
default 0x100000
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
default 64
endif # NORTHBRIDGE_AMD_AGESA_FAMILY14
diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig
index 3b66f56..5bb7cca 100644
--- a/src/northbridge/amd/agesa/family15tn/Kconfig
+++ b/src/northbridge/amd/agesa/family15tn/Kconfig
@@ -11,10 +11,10 @@
hex
default 0x100000
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
default 64
endif # NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig
index ee02865..8cf919a 100644
--- a/src/northbridge/amd/agesa/family16kb/Kconfig
+++ b/src/northbridge/amd/agesa/family16kb/Kconfig
@@ -11,10 +11,10 @@
hex
default 0x100000
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
default 64
config VGA_BIOS_ID
diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig
index c1fc9a8..27ae673 100644
--- a/src/northbridge/amd/pi/00730F01/Kconfig
+++ b/src/northbridge/amd/pi/00730F01/Kconfig
@@ -10,10 +10,10 @@
hex
default 0x100000
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
default 64
config VGA_BIOS_ID
diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig
index d9cf8af..c0711ee 100644
--- a/src/northbridge/intel/e7505/Kconfig
+++ b/src/northbridge/intel/e7505/Kconfig
@@ -7,7 +7,7 @@
config NORTHBRIDGE_SPECIFIC_OPTIONS
def_bool y
- select NO_MMCONF_SUPPORT
+ select NO_ECAM_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP
select NO_CBFS_MCACHE
select LEGACY_SMP_INIT
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index e3675db..3f632a1 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -23,10 +23,10 @@
string
default "8086,2a42"
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
int
default 64
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl
index 43d73e9..c4636be 100644
--- a/src/northbridge/intel/gm45/acpi/gm45.asl
+++ b/src/northbridge/intel/gm45/acpi/gm45.asl
@@ -16,7 +16,7 @@
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
+ Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index a9a1e8e..eb1aa0a 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -9,7 +9,7 @@
static uint32_t encode_pciexbar_length(void)
{
- switch (CONFIG_MMCONF_BUS_NUMBER) {
+ switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -21,17 +21,17 @@
{
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
+ * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to
* true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
+ * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
*/
- const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0);
pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32);
}
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 61c201a..50acb09a 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -32,10 +32,10 @@
string
default "8086,0166"
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
int
default 64
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 7dfae9f..513e960 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -125,7 +125,7 @@
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
+ // PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -161,7 +161,7 @@
}
PMIN = Local0
- PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
+ PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1
PLEN = (PMAX - PMIN) + 1
Return (MCRS)
@@ -178,7 +178,7 @@
Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE)
- Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
+ Memory32Fixed (ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT
Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM
Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index 1336582..03a715f 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -9,7 +9,7 @@
static uint32_t encode_pciexbar_length(void)
{
- switch (CONFIG_MMCONF_BUS_NUMBER) {
+ switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -21,15 +21,15 @@
{
/*
* The "io" variant of the config access is explicitly used to setup the
- * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
+ * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all
* subsequent non-explicit config accesses use MCFG. This code also assumes
* that bootblock_northbridge_init() is the first thing called in the non-asm
* boot block code. The final assumption is that no assembly code is using the
- * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
+ * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
- const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index 338b4d0..f71d117 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -349,7 +349,7 @@
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = CONFIG_FIXED_RCBA_MMIO_BASE,
diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
index 0fcadce..4b1638c 100644
--- a/src/northbridge/intel/i440bx/Kconfig
+++ b/src/northbridge/intel/i440bx/Kconfig
@@ -2,7 +2,7 @@
config NORTHBRIDGE_INTEL_I440BX
bool
- select NO_MMCONF_SUPPORT
+ select NO_ECAM_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP
select NO_CBFS_MCACHE
select LEGACY_SMP_INIT
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index ac19fcc..7a05d20 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -35,10 +35,10 @@
for the LVDS port. A linear framebuffer is only supported for
LVDS.
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
int
default 64
diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl
index 683ad37..f935b71 100644
--- a/src/northbridge/intel/i945/acpi/i945.asl
+++ b/src/northbridge/intel/i945/acpi/i945.asl
@@ -40,7 +40,7 @@
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
+ Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 448d5e4..1486a1b 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -9,7 +9,7 @@
static uint32_t encode_pciexbar_length(void)
{
- switch (CONFIG_MMCONF_BUS_NUMBER) {
+ switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -20,14 +20,16 @@
void bootblock_early_northbridge_init(void)
{
/*
- * The "io" variant of the config access is explicitly used to setup the PCIEXBAR
- * because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit
- * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is
- * the first thing called in the non-asm boot block code. The final assumption is that
- * no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
+ * The "io" variant of the config access is explicitly used to setup the
+ * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way
+ * all subsequent non-explicit config accesses use MCFG. This code also
+ * assumes that bootblock_northbridge_init() is the first thing called
+ * in the non-asm boot block code. The final assumption is that no
+ * assembly code is using the CONFIG(ECAM_MMCONF_SUPPORT) option to do
+ * PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
- const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}
diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
index 9fb7769..a614058 100644
--- a/src/northbridge/intel/ironlake/Kconfig
+++ b/src/northbridge/intel/ironlake/Kconfig
@@ -39,10 +39,10 @@
The amount of anticipated stack usage in CAR by bootblock and
other stages.
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
default 256
config INTEL_GMA_BCLV_OFFSET
diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl
index 098dd13..b4bd8e9 100644
--- a/src/northbridge/intel/ironlake/acpi/ironlake.asl
+++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl
@@ -14,7 +14,7 @@
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
+ Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c
index 241eb43..58f49da 100644
--- a/src/northbridge/intel/ironlake/bootblock.c
+++ b/src/northbridge/intel/ironlake/bootblock.c
@@ -10,7 +10,7 @@
static uint32_t encode_pciexbar_length(void)
{
/* NOTE: Ironlake uses a different encoding for the PCIEXBAR length field */
- switch (CONFIG_MMCONF_BUS_NUMBER) {
+ switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 6 << 1;
case 64: return 7 << 1;
@@ -27,7 +27,7 @@
*/
const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1);
- const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(qpi_sad, SAD_PCIEXBAR + 4, 0);
pci_io_write_config32(qpi_sad, SAD_PCIEXBAR, reg32);
}
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index 3fb1c10..9a8b21e 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -21,7 +21,7 @@
#include "memmap.h"
-#define QUICKPATH_BUS (CONFIG_MMCONF_BUS_NUMBER - 1)
+#define QUICKPATH_BUS (CONFIG_ECAM_MMCONF_BUS_NUMBER - 1)
#include <southbridge/intel/ibexpeak/pch.h>
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index f85cd2e..b2a0730 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -19,10 +19,10 @@
string
default "8086,a001"
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
int
default 256
diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl
index 4b74469..4901c21 100644
--- a/src/northbridge/intel/pineview/acpi/pineview.asl
+++ b/src/northbridge/intel/pineview/acpi/pineview.asl
@@ -15,7 +15,7 @@
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
+ Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c
index 61bd2ee..498d21a 100644
--- a/src/northbridge/intel/pineview/bootblock.c
+++ b/src/northbridge/intel/pineview/bootblock.c
@@ -8,7 +8,7 @@
static uint32_t encode_pciexbar_length(void)
{
- switch (CONFIG_MMCONF_BUS_NUMBER) {
+ switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -18,6 +18,6 @@
void bootblock_early_northbridge_init(void)
{
- const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index ae24690..3abbddf 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -83,12 +83,12 @@
string
default "8086,0106"
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
help
The MRC blob requires it to be at 0xf0000000.
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
int
default 64
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
index 977d7a7..4ce4cb6 100644
--- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
@@ -320,7 +320,7 @@
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
+ // PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -356,7 +356,7 @@
}
PMIN = Local0
- PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
+ PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1
PLEN = PMAX - PMIN + 1
Return (MCRS)
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index 1eba744..9e3708a 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -9,7 +9,7 @@
static uint32_t encode_pciexbar_length(void)
{
- switch (CONFIG_MMCONF_BUS_NUMBER) {
+ switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -21,15 +21,15 @@
{
/*
* The "io" variant of the config access is explicitly used to setup the
- * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
+ * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all
* subsequent non-explicit config accesses use MCFG. This code also assumes
* that bootblock_northbridge_init() is the first thing called in the non-asm
* boot block code. The final assumption is that no assembly code is using the
- * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
+ * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
- const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index ee5f1c9..186ab59 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -231,7 +231,7 @@
pei_data->mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE;
pei_data->dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE;
pei_data->epbar = CONFIG_FIXED_EPBAR_MMIO_BASE;
- pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS;
+ pei_data->pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
pei_data->hpet_address = CONFIG_HPET_ADDRESS;
pei_data->thermalbase = 0xfed08000;
pei_data->system_type = !(get_platform_type() == PLATFORM_MOBILE);
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 8eda090..5318623 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -21,10 +21,10 @@
string
default "8086,2e32"
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
int
default 256
diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl
index 8ef0ca4..462cdf9 100644
--- a/src/northbridge/intel/x4x/acpi/x4x.asl
+++ b/src/northbridge/intel/x4x/acpi/x4x.asl
@@ -13,7 +13,7 @@
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
+ Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index f15d181..80375a7 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -10,7 +10,7 @@
static uint32_t encode_pciexbar_length(void)
{
- switch (CONFIG_MMCONF_BUS_NUMBER) {
+ switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -23,6 +23,6 @@
/* Disable LaGrande Technology (LT) */
read32((void *)TPM_BASE_ADDRESS);
- const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);
}