| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2006 AMD |
| ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD. |
| ## |
| ## Copyright (C) 2006 MSI |
| ## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI. |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; either version 2 of the License, or |
| ## (at your option) any later version. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| ## You should have received a copy of the GNU General Public License |
| ## along with this program; if not, write to the Free Software |
| ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| ## |
| |
| ## CONFIG_XIP_ROM_SIZE must be a power of 2. |
| default CONFIG_XIP_ROM_SIZE = 64 * 1024 |
| include /config/nofailovercalculation.lb |
| default CONFIG_ROM_PAYLOAD = 1 |
| |
| arch i386 end |
| |
| |
| ## |
| ## Build the objects we have code for in this directory. |
| ## |
| |
| driver mainboard.o |
| |
| #dir /drivers/ati/ragexl |
| #needed by irq_tables and mptable and acpi_tables |
| object get_bus_conf.o |
| |
| |
| if CONFIG_GENERATE_MP_TABLE object mptable.o end |
| if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end |
| |
| if CONFIG_USE_INIT |
| |
| makerule ./auto.o |
| depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" |
| end |
| |
| else |
| |
| makerule ./auto.inc |
| depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" |
| action "perl -e 's/\.rodata/.rom.data/g' -pi $@" |
| action "perl -e 's/\.text/.section .rom.text/g' -pi $@" |
| end |
| |
| end |
| |
| ## |
| ## Build our 16 bit and 32 bit coreboot entry code |
| ## |
| if CONFIG_USE_FALLBACK_IMAGE |
| mainboardinit cpu/x86/16bit/entry16.inc |
| ldscript /cpu/x86/16bit/entry16.lds |
| end |
| |
| mainboardinit cpu/x86/32bit/entry32.inc |
| |
| if CONFIG_USE_INIT |
| ldscript /cpu/x86/32bit/entry32.lds |
| end |
| |
| if CONFIG_USE_INIT |
| ldscript /cpu/amd/car/cache_as_ram.lds |
| end |
| |
| ## |
| ## Build our reset vector (This is where coreboot is entered) |
| ## |
| if CONFIG_USE_FALLBACK_IMAGE |
| mainboardinit cpu/x86/16bit/reset16.inc |
| ldscript /cpu/x86/16bit/reset16.lds |
| else |
| mainboardinit cpu/x86/32bit/reset32.inc |
| ldscript /cpu/x86/32bit/reset32.lds |
| end |
| |
| ## |
| ## Include an id string (For safe flashing) |
| ## |
| mainboardinit arch/i386/lib/id.inc |
| ldscript /arch/i386/lib/id.lds |
| |
| ## |
| ## ROMSTRAP table for MCP55 |
| ## |
| if CONFIG_USE_FALLBACK_IMAGE |
| mainboardinit southbridge/nvidia/mcp55/romstrap.inc |
| ldscript /southbridge/nvidia/mcp55/romstrap.lds |
| end |
| |
| ## |
| ## Setup Cache-As-Ram |
| ## |
| mainboardinit cpu/amd/car/cache_as_ram.inc |
| |
| ### |
| ### This is the early phase of coreboot startup |
| ### Things are delicate and we test to see if we should |
| ### failover to another image. |
| ### |
| if CONFIG_USE_FALLBACK_IMAGE |
| ldscript /arch/i386/lib/failover.lds |
| end |
| |
| ### |
| ### O.k. We aren't just an intermediary anymore! |
| ### |
| |
| ## |
| ## Setup RAM |
| ## |
| if CONFIG_USE_INIT |
| initobject auto.o |
| else |
| mainboardinit ./auto.inc |
| end |
| |
| ## |
| ## Include the secondary Configuration files |
| ## |
| config chip.h |
| |
| |
| # sample config for msi/ms9282 |
| chip northbridge/amd/amdk8/root_complex |
| device apic_cluster 0 on |
| chip cpu/amd/socket_F |
| device apic 0 on end |
| end |
| end |
| |
| device pci_domain 0 on |
| chip northbridge/amd/amdk8 #mc0 |
| device pci 18.0 on # northbridge |
| # devices on link 0, link 0 == LDT 0 |
| chip southbridge/nvidia/mcp55 |
| device pci 0.0 on end # HT |
| device pci 1.0 on # LPC |
| chip superio/winbond/w83627ehg |
| device pnp 2e.0 on # Floppy |
| io 0x60 = 0x3f0 |
| irq 0x70 = 6 |
| drq 0x74 = 2 |
| end |
| device pnp 2e.1 off # Parallel Port |
| io 0x60 = 0x378 |
| irq 0x70 = 7 |
| end |
| device pnp 2e.2 on # Com1 |
| io 0x60 = 0x3f8 |
| irq 0x70 = 4 |
| end |
| device pnp 2e.3 off # Com2 |
| io 0x60 = 0x2f8 |
| irq 0x70 = 3 |
| end |
| device pnp 2e.5 on # Keyboard |
| io 0x60 = 0x60 |
| io 0x62 = 0x64 |
| irq 0x70 = 1 |
| irq 0x72 = 12 |
| end |
| device pnp 2e.6 off # SERIAL_FALSH |
| io 0x60 = 0x100 |
| end |
| device pnp 2e.7 off # GAME_MIDI_GIPO1 |
| io 0x60 = 0x220 |
| io 0x62 = 0x300 |
| irq 0x70 = 9 |
| end |
| device pnp 2e.8 off end # WDTO_PLED |
| device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5 |
| device pnp 2e.a off end # ACPI |
| device pnp 2e.b on # HW Monitor |
| io 0x60 = 0x290 |
| irq 0x70 = 5 |
| end |
| end |
| end |
| device pci 1.1 on # SM 0 |
| chip drivers/i2c/i2cmux2 # pca9554 smbus mux |
| device i2c 70 on #0 pca9554 1 |
| chip drivers/generic/generic #dimm 0-0-0 |
| device i2c 50 on end |
| end |
| chip drivers/generic/generic #dimm 0-0-1 |
| device i2c 51 on end |
| end |
| chip drivers/generic/generic #dimm 0-1-0 |
| device i2c 52 on end |
| end |
| chip drivers/generic/generic #dimm 0-1-1 |
| device i2c 53 on end |
| end |
| chip drivers/generic/generic #dimm 0-0-0 |
| device i2c 54 on end |
| end |
| chip drivers/generic/generic #dimm 0-0-1 |
| device i2c 55 on end |
| end |
| chip drivers/generic/generic #dimm 0-1-0 |
| device i2c 56 on end |
| end |
| chip drivers/generic/generic #dimm 0-1-1 |
| device i2c 57 on end |
| end |
| end |
| device i2c 70 on #0 pca9554 2 |
| chip drivers/generic/generic #dimm 0-0-0 |
| device i2c 50 on end |
| end |
| chip drivers/generic/generic #dimm 0-0-1 |
| device i2c 51 on end |
| end |
| chip drivers/generic/generic #dimm 0-1-0 |
| device i2c 52 on end |
| end |
| chip drivers/generic/generic #dimm 0-1-1 |
| device i2c 53 on end |
| end |
| chip drivers/generic/generic #dimm 0-0-0 |
| device i2c 54 on end |
| end |
| chip drivers/generic/generic #dimm 0-0-1 |
| device i2c 55 on end |
| end |
| chip drivers/generic/generic #dimm 0-1-0 |
| device i2c 56 on end |
| end |
| chip drivers/generic/generic #dimm 0-1-1 |
| device i2c 57 on end |
| end |
| end |
| end |
| end |
| device pci 1.1 on # SM 1 |
| chip drivers/i2c/i2cmux2 # pca9554 smbus mux |
| device i2c 72 on #pca9554 channle1 |
| chip drivers/i2c/adm1027 #HWM ADT7476 1 |
| device i2c 2e on end |
| end |
| end |
| device i2c 72 on #pca9545 channel 2 |
| chip drivers/i2c/adm1027 #HWM ADT7463 |
| device i2c 2e on end |
| end |
| end |
| device i2c 72 on end #pca9545 channel 3 |
| device i2c 72 on #pca9545 channel 4 |
| chip drivers/i2c/adm1027 #HWM ADT7476 2 |
| device i2c 2e on end |
| end |
| end |
| end |
| end |
| |
| device pci 2.0 on end # USB 1.1 |
| device pci 2.1 on end # USB 2 |
| device pci 4.0 on end # IDE |
| device pci 5.0 on end # SATA 0 |
| device pci 5.1 on end # SATA 1 |
| device pci 5.2 on end # SATA 2 |
| device pci 6.0 on #P2P |
| device pci 4.0 on end |
| end # P2P |
| device pci 7.0 on end # reserve |
| device pci 8.0 on end # MAC0 |
| device pci 9.0 on end # MAC1 |
| device pci a.0 on |
| device pci 0.0 on |
| device pci 4.0 on end #pci_E lan1 |
| device pci 4.1 on end #pci_E lan2 |
| end |
| end # 0x376 |
| device pci b.0 on end # PCI E 0x374 |
| device pci c.0 on end |
| device pci d.0 on #SAS |
| device pci 0.0 on end |
| end # PCI E 1 0x378 |
| device pci e.0 on end # PCI E 0 0x375 |
| device pci f.0 on end #PCI E 0x377 pci_E slot |
| register "ide0_enable" = "1" |
| register "ide1_enable" = "1" |
| register "sata0_enable" = "1" |
| register "sata1_enable" = "1" |
| end |
| end # device pci 18.0 |
| device pci 18.0 on end # Link 1 |
| device pci 18.0 on end |
| device pci 18.1 on end |
| device pci 18.2 on end |
| device pci 18.3 on end |
| end #mc0 |
| |
| end # pci_domain |
| |
| # chip drivers/generic/debug |
| # device pnp 0.0 off end |
| # device pnp 0.1 off end |
| # device pnp 0.2 off end |
| # device pnp 0.3 off end |
| # device pnp 0.4 off end |
| # device pnp 0.5 on end |
| # end |
| end # root_complex |