| config SOC_INTEL_METEORLAKE |
| bool |
| help |
| Intel Meteorlake support |
| |
| if SOC_INTEL_METEORLAKE |
| |
| config CPU_SPECIFIC_OPTIONS |
| def_bool y |
| select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
| select ARCH_X86 |
| select BOOT_DEVICE_SUPPORTS_WRITES |
| select CACHE_MRC_SETTINGS |
| select CPU_INTEL_COMMON |
| select CPU_INTEL_COMMON_VOLTAGE |
| select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| select CPU_SUPPORTS_INTEL_TME |
| select CPU_SUPPORTS_PM_TIMER_EMULATION |
| select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS |
| select DEFAULT_X2APIC_LATE_WORKAROUND |
| select DISPLAY_FSP_VERSION_INFO_2 |
| select DRIVERS_USB_ACPI |
| select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 |
| select FSP_COMPRESS_FSP_S_LZ4 |
| select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
| select FSP_M_XIP |
| select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
| select FSP_USES_CB_DEBUG_EVENT_HANDLER |
| select FSPS_HAS_ARCH_UPD |
| select GENERIC_GPIO_LIB |
| select HAVE_DEBUG_RAM_SETUP |
| select HAVE_FSP_GOP |
| select HAVE_HYPERTHREADING |
| select HAVE_INTEL_COMPLIANCE_TEST_MODE |
| select HAVE_SMI_HANDLER |
| select IDT_IN_EVERY_STAGE |
| select INTEL_DESCRIPTOR_MODE_CAPABLE |
| select INTEL_GMA_ACPI |
| select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| select INTEL_GMA_OPREGION_2_1 |
| select IOAPIC |
| select MICROCODE_BLOB_UNDISCLOSED |
| select MP_SERVICES_PPI_V2 |
| select MRC_SETTINGS_PROTECT |
| select PARALLEL_MP_AP_WORK |
| select PLATFORM_USES_FSP2_3 |
| select PMC_GLOBAL_RESET_ENABLE_LOCK |
| select SOC_INTEL_COMMON |
| select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| select SOC_INTEL_COMMON_BLOCK |
| select SOC_INTEL_COMMON_BLOCK_ACPI |
| select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
| select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID |
| select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
| select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
| select SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
| select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ |
| select SOC_INTEL_COMMON_BLOCK_CAR |
| select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
| select SOC_INTEL_COMMON_BLOCK_CNVI |
| select SOC_INTEL_COMMON_BLOCK_CPU |
| select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
| select SOC_INTEL_COMMON_BLOCK_DTT |
| select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
| select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR |
| select SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS |
| select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| select SOC_INTEL_COMMON_BLOCK_HDA |
| select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC |
| select SOC_INTEL_COMMON_BLOCK_IPU |
| select SOC_INTEL_COMMON_BLOCK_IOE_P2SB |
| select SOC_INTEL_COMMON_BLOCK_IRQ |
| select SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 |
| select SOC_INTEL_COMMON_BLOCK_MEMINIT |
| select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 |
| select SOC_INTEL_COMMON_BLOCK_PMC_EPOC |
| select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
| select SOC_INTEL_COMMON_BLOCK_SA |
| select SOC_INTEL_COMMON_BLOCK_SMM |
| select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
| select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC |
| select SOC_INTEL_COMMON_BLOCK_XHCI |
| select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
| select SOC_INTEL_COMMON_BASECODE |
| select SOC_INTEL_COMMON_FSP_RESET |
| select SOC_INTEL_COMMON_PCH_CLIENT |
| select SOC_INTEL_COMMON_RESET |
| select SOC_INTEL_COMMON_BLOCK_IOC |
| select SOC_INTEL_CSE_SEND_EOP_LATE |
| select SOC_INTEL_CSE_SET_EOP |
| select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO |
| select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION |
| select SSE2 |
| select SUPPORT_CPU_UCODE_IN_CBFS |
| select TSC_MONOTONIC_TIMER |
| select UDELAY_TSC |
| select UDK_202111_BINDING |
| select X86_INIT_NEED_1_SIPI |
| |
| config SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT |
| bool |
| default y |
| select SOC_INTEL_COMMON_BLOCK_TCSS |
| select SOC_INTEL_COMMON_BLOCK_USB4 |
| select SOC_INTEL_COMMON_BLOCK_USB4_PCIE |
| select SOC_INTEL_COMMON_BLOCK_USB4_XHCI |
| |
| config METEORLAKE_CAR_ENHANCED_NEM |
| bool |
| default y if !INTEL_CAR_NEM |
| select INTEL_CAR_NEM_ENHANCED |
| select CAR_HAS_SF_MASKS |
| select COS_MAPPED_TO_MSB |
| select CAR_HAS_L3_PROTECTED_WAYS |
| |
| config MAX_CPUS |
| int |
| default 22 |
| |
| config DCACHE_RAM_BASE |
| default 0xfef00000 |
| |
| config DCACHE_RAM_SIZE |
| default 0xc0000 |
| help |
| The size of the cache-as-ram region required during bootblock |
| and/or romstage. |
| |
| config DCACHE_BSP_STACK_SIZE |
| hex |
| default 0x80400 |
| help |
| The amount of anticipated stack usage in CAR by bootblock and |
| other stages. In the case of FSP_USES_CB_STACK default value will be |
| sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement |
| (~1KiB). |
| |
| config FSP_TEMP_RAM_SIZE |
| hex |
| default 0x20000 |
| help |
| The amount of anticipated heap usage in CAR by FSP. |
| Refer to Platform FSP integration guide document to know |
| the exact FSP requirement for Heap setup. |
| |
| config CHIPSET_DEVICETREE |
| string |
| default "soc/intel/meteorlake/chipset.cb" |
| |
| config EXT_BIOS_WIN_BASE |
| default 0xf8000000 |
| |
| config EXT_BIOS_WIN_SIZE |
| default 0x2000000 |
| |
| config IFD_CHIPSET |
| string |
| default "mtl" |
| |
| config IED_REGION_SIZE |
| hex |
| default 0x400000 |
| |
| config HEAP_SIZE |
| hex |
| default 0x10000 |
| |
| # Intel recommends reserving the PCIe TBT root port resources as below: |
| # - 42 buses |
| # - 194 MiB Non-prefetchable memory |
| # - 448 MiB Prefetchable memory |
| if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
| |
| config PCIEXP_HOTPLUG_BUSES |
| int |
| default 42 |
| |
| config PCIEXP_HOTPLUG_MEM |
| hex |
| default 0xc200000 |
| |
| config PCIEXP_HOTPLUG_PREFETCH_MEM |
| hex |
| default 0x1c000000 |
| |
| endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
| |
| config MAX_TBT_ROOT_PORTS |
| int |
| default 4 |
| |
| config MAX_ROOT_PORTS |
| int |
| default 12 |
| |
| config MAX_PCIE_CLOCK_SRC |
| int |
| default 9 |
| |
| config SMM_TSEG_SIZE |
| hex |
| default 0x800000 |
| |
| config SMM_RESERVED_SIZE |
| hex |
| default 0x200000 |
| |
| config PCR_BASE_ADDRESS |
| hex |
| default 0xe0000000 |
| help |
| This option allows you to select MMIO Base Address of sideband bus. |
| |
| config ECAM_MMCONF_BASE_ADDRESS |
| default 0xc0000000 |
| |
| config SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR |
| int |
| default 125 |
| |
| config SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR |
| int |
| default 100 |
| |
| config CPU_BCLK_MHZ |
| int |
| default 100 |
| |
| config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| int |
| default 120 |
| |
| config CPU_XTAL_HZ |
| default 38400000 |
| |
| config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| int |
| default 133 |
| |
| config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| int |
| default 3 |
| |
| config SOC_INTEL_I2C_DEV_MAX |
| int |
| default 6 |
| |
| config SOC_INTEL_UART_DEV_MAX |
| int |
| default 3 |
| |
| config SOC_INTEL_USB2_DEV_MAX |
| int |
| default 10 |
| |
| config SOC_INTEL_USB3_DEV_MAX |
| int |
| default 2 |
| |
| config CONSOLE_UART_BASE_ADDRESS |
| hex |
| default 0xfe02c000 |
| depends on INTEL_LPSS_UART_FOR_CONSOLE |
| |
| config VBT_DATA_SIZE_KB |
| int |
| default 9 |
| |
| # Clock divider parameters for 115200 baud rate |
| # Baudrate = (UART source clock * M) /(N *16) |
| # MTL UART source clock: 100MHz |
| config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| hex |
| default 0x25a |
| |
| config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| hex |
| default 0x7fff |
| |
| config VBOOT |
| select VBOOT_SEPARATE_VERSTAGE |
| select VBOOT_MUST_REQUEST_DISPLAY |
| select VBOOT_STARTS_IN_BOOTBLOCK |
| select VBOOT_VBNV_CMOS |
| select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| select VBOOT_X86_SHA256_ACCELERATION |
| |
| # Default hash block size is 1KiB. Increasing it to 4KiB to improve |
| # hashing time as well as read time. |
| config VBOOT_HASH_BLOCK_SIZE |
| hex |
| default 0x1000 |
| |
| config CBFS_SIZE |
| hex |
| default 0x200000 |
| |
| config PRERAM_CBMEM_CONSOLE_SIZE |
| hex |
| default 0x16000 if CONSOLE_SERIAL |
| default 0x2000 |
| |
| config CONSOLE_CBMEM_BUFFER_SIZE |
| hex |
| default 0x100000 if CONSOLE_SERIAL |
| default 0x40000 |
| |
| config FSP_HEADER_PATH |
| string "Location of FSP headers" |
| default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/" |
| |
| config FSP_FD_PATH |
| string |
| depends on FSP_USE_REPO |
| default "3rdparty/fsp/MeteorLakeFspBinPkg/Fsp.fd" |
| |
| config SOC_INTEL_METEORLAKE_DEBUG_CONSENT |
| int "Debug Consent for MTL" |
| # USB DBC is more common for developers so make this default to 3 if |
| # SOC_INTEL_DEBUG_CONSENT=y |
| default 3 if SOC_INTEL_DEBUG_CONSENT |
| default 0 |
| help |
| This is to control debug interface on SOC. |
| Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| PlatformDebugConsent in FspmUpd.h has the details. |
| |
| Desired platform debug type are |
| 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 6:Enable (2-wire DCI OOB), 7:Manual |
| |
| config DATA_BUS_WIDTH |
| int |
| default 128 |
| |
| config DIMMS_PER_CHANNEL |
| int |
| default 2 |
| |
| config MRC_CHANNEL_WIDTH |
| int |
| default 16 |
| |
| config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET |
| hex |
| default 0x800000 |
| |
| config FSP_PUBLISH_MBP_HOB |
| bool |
| default n if CHROMEOS |
| default y |
| help |
| This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. |
| Disabling it for the platforms, which do not use MBP HOB, can improve the boot time. |
| |
| endif |