cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCK
Console is not yet enabled in bootblock. This will be done in
a different CL.
Change-Id: Ic751d42a1969fb79fb50366f766d8796846a0bc4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index 23df701..5262b18 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -18,14 +18,10 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#if !CONFIG(ROMCC_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
-#else
-#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
-#endif
.global bootblock_pre_c_entry
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index 00af79a..7919974 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -27,7 +27,6 @@
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select UNKNOWN_TSC_RATE
- select ROMCC_BOOTBLOCK
config DCACHE_RAM_BASE
hex
@@ -37,4 +36,12 @@
hex
default 0x02000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x1000
+
+config C_ENV_BOOTBLOCK_SIZE
+ hex
+ default 0x2000
+
endif
diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc
index 599a5d0..0e4e7e6 100644
--- a/src/cpu/intel/slot_1/Makefile.inc
+++ b/src/cpu/intel/slot_1/Makefile.inc
@@ -26,6 +26,7 @@
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
-cpu_incs-y += $(src)/cpu/intel/car/p3/cache_as_ram.S
+bootblock-y += ../car/p3/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c
diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
index df1e365..010a6e7 100644
--- a/src/northbridge/intel/i440bx/Kconfig
+++ b/src/northbridge/intel/i440bx/Kconfig
@@ -17,6 +17,7 @@
bool
select NO_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP
+ select NO_BOOTBLOCK_CONSOLE
config SDRAMPWR_4DIMM
bool
diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig
index f5b5f4e..d0eec0e 100644
--- a/src/southbridge/intel/i82371eb/Kconfig
+++ b/src/southbridge/intel/i82371eb/Kconfig
@@ -4,8 +4,3 @@
select SOUTHBRIDGE_INTEL_COMMON_RTC
select SOUTHBRIDGE_INTEL_COMMON_RESET
bool
-
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/intel/i82371eb/bootblock.c"
- depends on SOUTHBRIDGE_INTEL_I82371EB
diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc
index 131010f..390fd97 100644
--- a/src/southbridge/intel/i82371eb/Makefile.inc
+++ b/src/southbridge/intel/i82371eb/Makefile.inc
@@ -16,6 +16,8 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y)
+bootblock-y += bootblock.c
+
ramstage-y += i82371eb.c
ramstage-y += isa.c
ramstage-y += ide.c
diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c
index 2b8cd1f..a6d62e0 100644
--- a/src/southbridge/intel/i82371eb/bootblock.c
+++ b/src/southbridge/intel/i82371eb/bootblock.c
@@ -18,6 +18,7 @@
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <device/pci_type.h>
+#include <cpu/intel/car/bootblock.h>
#include "i82371eb.h"
#define PCI_ID(VENDOR_ID, DEVICE_ID) \
@@ -34,7 +35,13 @@
return PCI_DEV_INVALID;
}
-static void bootblock_southbridge_init(void)
+/* TODO: Does not need to happen before console init. */
+/* The whole rom is not accessible before this so limit
+ the bootblock size. */
+#if CONFIG_C_ENV_BOOTBLOCK_SIZE > 0x10000
+#error "CONFIG_C_ENV_BOOTBLOCK_SIZE needs to be below 64KiB"
+#endif
+void bootblock_early_southbridge_init(void)
{
u16 reg16;
pci_devfn_t dev;