| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| |
| config CPU_INTEL_SLOT_1 |
| bool |
| |
| if CPU_INTEL_SLOT_1 |
| |
| config SLOT_SPECIFIC_OPTIONS # dummy |
| def_bool y |
| select CPU_INTEL_MODEL_65X |
| select CPU_INTEL_MODEL_67X |
| select CPU_INTEL_MODEL_68X |
| select CPU_INTEL_MODEL_6BX |
| select CPU_INTEL_MODEL_6XX |
| select NO_SMM |
| select UDELAY_TSC |
| select TSC_MONOTONIC_TIMER |
| select UNKNOWN_TSC_RATE |
| |
| config DCACHE_RAM_BASE |
| hex |
| default 0xfefc0000 |
| |
| config DCACHE_RAM_SIZE |
| hex |
| default 0x02000 |
| |
| config DCACHE_BSP_STACK_SIZE |
| hex |
| default 0x1000 |
| |
| config C_ENV_BOOTBLOCK_SIZE |
| hex |
| default 0x2000 |
| |
| endif |