commit 17c59f5da533eddef5e6bb85866b6d933e7fb767
author Elyes HAOUAS <ehaouas@noos.fr> Sun May 13 13:38:38 2018 +0200
committer Kyösti Mälkki <kyosti.malkki@gmail.com> Wed May 23 05:20:25 2018 +0000
tree 2ed9e29d7d45779c00b689cf063d3b9506c94ee0
parent 5af546c5e40835145fee6eff4f43283bea80db91

sb/intel/i82870: Get rid of device_t

Use of device_t has been abandoned in ramstage.

Change-Id: I751b72733de2e3bf3aebd1bc85dc83ec1c406faa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/southbridge/intel/i82870/ioapic.c

diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index da7da5e..6c653015 100644
--- a/src/southbridge/intel/i82870/ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
@@ -9,7 +9,7 @@
 
 static int num_p64h2_ioapics = 0;
 
-static void p64h2_ioapic_enable(device_t dev)
+static void p64h2_ioapic_enable(struct device *dev)
 {
 	/* We have to enable MEM and Bus Master for IOAPIC */
 	uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
@@ -26,7 +26,7 @@
  * @param dev PCI bus/device/function of P64H2 IOAPIC.
  *            NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0.
  */
-static void p64h2_ioapic_init(device_t dev)
+static void p64h2_ioapic_init(struct device *dev)
 {
 	uint32_t memoryBase;
 	int apic_index, apic_id;

src/southbridge/intel/i82870/pcibridge.c

diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c
index e8d890a..01cdd14 100644
--- a/src/southbridge/intel/i82870/pcibridge.c
+++ b/src/southbridge/intel/i82870/pcibridge.c
@@ -6,7 +6,7 @@
 #include <pc80/mc146818rtc.h>
 #include "82870.h"
 
-static void p64h2_pcix_init(device_t dev)
+static void p64h2_pcix_init(struct device *dev)
 {
 	u32 dword;
 	u8 byte;