diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index da7da5e..6c653015 100644
--- a/src/southbridge/intel/i82870/ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
@@ -9,7 +9,7 @@
 
 static int num_p64h2_ioapics = 0;
 
-static void p64h2_ioapic_enable(device_t dev)
+static void p64h2_ioapic_enable(struct device *dev)
 {
 	/* We have to enable MEM and Bus Master for IOAPIC */
 	uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
@@ -26,7 +26,7 @@
  * @param dev PCI bus/device/function of P64H2 IOAPIC.
  *            NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0.
  */
-static void p64h2_ioapic_init(device_t dev)
+static void p64h2_ioapic_init(struct device *dev)
 {
 	uint32_t memoryBase;
 	int apic_index, apic_id;
diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c
index e8d890a..01cdd14 100644
--- a/src/southbridge/intel/i82870/pcibridge.c
+++ b/src/southbridge/intel/i82870/pcibridge.c
@@ -6,7 +6,7 @@
 #include <pc80/mc146818rtc.h>
 #include "82870.h"
 
-static void p64h2_pcix_init(device_t dev)
+static void p64h2_pcix_init(struct device *dev)
 {
 	u32 dword;
 	u8 byte;