blob: 90b64669b30ffcaff485d897f60f4ae45702e65e [file] [log] [blame]
Paul Menzel26285712017-04-17 10:57:51 +02001/*
2 * Intel ACPI Component Architecture
3 * AML/ASL+ Disassembler version 20160831-64
4 * Copyright (c) 2000 - 2016 Intel Corporation
5 *
6 * Disassembling to symbolic ASL+ operators
7 *
8 * Disassembly of ssdt1.dat, Mon Jan 2 15:19:14 2017
9 *
10 * Original Table Header:
11 * Signature "SSDT"
12 * Length 0x00000214 (532)
13 * Revision 0x01
14 * Checksum 0x0C
15 * OEM ID "AMI"
16 * OEM Table ID "CPU1PM"
17 * OEM Revision 0x00000001 (1)
18 * Compiler ID "INTL"
19 * Compiler Version 0x20060113 (537264403)
20 */
21DefinitionBlock ("", "SSDT", 1, "AMI", "CPU1PM", 0x00000001)
22{
23 External (_PR_.CPU1, DeviceObj)
24 External (CFGD, UnknownObj)
25 External (NCPU, UnknownObj)
26 External (TYPE, UnknownObj)
27
28 Scope (\_PR.CPU1)
29 {
30 Name (NPCT, Package (0x02)
31 {
32 ResourceTemplate ()
33 {
34 Register (FFixedHW,
35 0x40, // Bit Width
36 0x00, // Bit Offset
37 0x0000000000000199, // Address
38 ,)
39 },
40
41 ResourceTemplate ()
42 {
43 Register (FFixedHW,
44 0x10, // Bit Width
45 0x00, // Bit Offset
46 0x0000000000000198, // Address
47 ,)
48 }
49 })
50 Name (SPCT, Package (0x02)
51 {
52 ResourceTemplate ()
53 {
54 Register (SystemIO,
55 0x10, // Bit Width
56 0x00, // Bit Offset
57 0x0000000000000900, // Address
58 ,)
59 },
60
61 ResourceTemplate ()
62 {
63 Register (SystemIO,
64 0x10, // Bit Width
65 0x00, // Bit Offset
66 0x0000000000000902, // Address
67 ,)
68 }
69 })
70 Method (_PCT, 0, NotSerialized) // _PCT: Performance Control
71 {
72 If ((TYPE & 0x01) == 0x01)
73 {
74 Return (NPCT) /* \_PR_.CPU1.NPCT */
75 }
76 Else
77 {
78 Return (SPCT) /* \_PR_.CPU1.SPCT */
79 }
80 }
81
82 Name (XPSS, 0x03)
83 Name (_PPC, 0x00) // _PPC: Performance Present Capabilities
84 Name (SPSS, Package (0x03)
85 {
86 Package (0x06)
87 {
88 0x000007D0,
89 0x000157C0,
90 0x0000006E,
91 0x0000000A,
92 0x00000086,
93 0x00000000
94 },
95
96 Package (0x06)
97 {
98 0x00000640,
99 0x00011880,
100 0x0000006E,
101 0x0000000A,
102 0x00000186,
103 0x00000001
104 },
105
106 Package (0x06)
107 {
108 0x000004B0,
109 0x0000E0D0,
110 0x0000006E,
111 0x0000000A,
112 0x00000286,
113 0x00000002
114 }
115 })
116 Name (NPSS, Package (0x03)
117 {
118 Package (0x06)
119 {
120 0x000007D0,
121 0x000157C0,
122 0x0000000A,
123 0x0000000A,
124 0x00000A27,
125 0x00000A27
126 },
127
128 Package (0x06)
129 {
130 0x00000640,
131 0x00011880,
132 0x0000000A,
133 0x0000000A,
134 0x00000822,
135 0x00000822
136 },
137
138 Package (0x06)
139 {
140 0x000004B0,
141 0x0000E0D0,
142 0x0000000A,
143 0x0000000A,
144 0x0000061D,
145 0x0000061D
146 }
147 })
148 Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States
149 {
150 If ((TYPE & 0x01) == 0x01)
151 {
152 Return (NPSS) /* \_PR_.CPU1.NPSS */
153 }
154 Else
155 {
156 Return (SPSS) /* \_PR_.CPU1.SPSS */
157 }
158 }
159
160 Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies
161 {
162 If (CFGD & 0x01000000)
163 {
164 If (TYPE & 0x0800)
165 {
166 Return (Package (0x01)
167 {
168 Package (0x05)
169 {
170 0x05,
171 0x00,
172 0x00,
173 0xFE,
174 NCPU
175 }
176 })
177 }
178
179 Return (Package (0x01)
180 {
181 Package (0x05)
182 {
183 0x05,
184 0x00,
185 0x00,
186 0xFC,
187 NCPU
188 }
189 })
190 }
191
192 Return (Package (0x01)
193 {
194 Package (0x05)
195 {
196 0x05,
197 0x00,
198 0x00,
199 0xFC,
200 NCPU
201 }
202 })
203 }
204 }
205}
206