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review.coreboot.org / board-status / b3431977e3661ed0c501df06113f5d01b4c9298e / . / asrock / e350m1 / 4.5-1198-ga0b15f44c9 / 2017-03-10T08_12_23Z / coreboot_console.txt
blob: 2d348985d77dba6a9df756daeaa91cfb1fb5f65c [file] [log] [blame]
coreboot-4.5-1198-ga0b15f44c9 Fri Mar 10 08:12:23 UTC 2017 ramstage starting...
BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
SB800 - Smbus.c - alink_ab_indx - Start.
SB800 - Smbus.c - alink_ab_indx - End.
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 17 exit 0
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 0
PNP: 002e.107: enabled 0
PNP: 002e.207: enabled 0
PNP: 002e.307: enabled 1
PNP: 002e.407: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 1
PNP: 002e.109: enabled 0
PNP: 002e.209: enabled 0
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 1
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PNP: 002e.d: enabled 1
PNP: 002e.e: enabled 0
PNP: 002e.f: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:15.1: enabled 1
PCI: 00:15.2: enabled 1
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 0
PNP: 002e.107: enabled 0
PNP: 002e.207: enabled 0
PNP: 002e.307: enabled 1
PNP: 002e.407: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 1
PNP: 002e.109: enabled 0
PNP: 002e.209: enabled 0
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 1
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PNP: 002e.d: enabled 1
PNP: 002e.e: enabled 0
PNP: 002e.f: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:15.1: enabled 1
PCI: 00:15.2: enabled 1
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
Mainboard E350M1 Enable.
Root Device scanning...
root_dev_scan_bus for Root Device
setup_bsp_ramtop, TOP MEM: msr.lo = 0xe0000000, msr.hi = 0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x1f000000, msr.hi = 0x00000002
setup_uma_memory: uma size 0x18000000, memory start 0xc8000000
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 scanning...
AP siblings=1
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
scan_bus: scanning of bus CPU_CLUSTER: 0 took 9 usecs
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [1022/1510] ops
PCI: 00:00.0 [1022/1510] enabled
PCI: 00:01.0 [1002/9802] enabled
PCI: 00:01.1 [1002/1314] enabled
PCI: Static device PCI: 00:04.0 not found, disabling it.
PCI: 00:11.0 [1002/4390] enabled
PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
IOAPIC: Clearing IOAPIC at fec00000
IOAPIC: 24 interrupts
IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: Dumping registers
reg 0x0000: 0x02000000
reg 0x0001: 0x00178021
reg 0x0002: 0x02000000
IOAPIC: 24 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
PCI: 00:14.0 [1002/4385] enabled
PCI: Static device PCI: 00:14.1 not found, disabling it.
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
PCI: 00:14.4 [1002/4384] enabled
PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:15.0 subordinate bus PCI Express
PCI: 00:15.0 [1002/43a0] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:15.1 subordinate bus PCI Express
PCI: 00:15.1 [1002/43a1] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:15.2 subordinate bus PCI Express
PCI: 00:15.2 [1002/43a2] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:15.3 subordinate bus PCI Express
PCI: 00:15.3 [1002/43a3] disabled
PCI: 00:16.0 [1002/4397] ops
PCI: 00:16.0 [1002/4397] disabled
PCI: 00:18.0 [1022/1700] enabled
PCI: 00:18.1 [1022/1701] enabled
PCI: 00:18.2 [1022/1702] enabled
PCI: 00:18.3 [1022/1703] enabled
PCI: 00:18.4 [1022/1704] enabled
PCI: 00:18.5 [1022/1718] enabled
PCI: 00:18.6 [1022/1716] enabled
PCI: 00:18.7 [1022/1719] enabled
PCI: 00:14.3 scanning...
scan_lpc_bus for PCI: 00:14.3
PNP: 002e.0 disabled
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 disabled
PNP: 002e.5 enabled
PNP: 002e.6 disabled
PNP: 002e.107 disabled
PNP: 002e.207 disabled
PNP: 002e.307 enabled
PNP: 002e.407 disabled
PNP: 002e.8 disabled
PNP: 002e.9 enabled
PNP: 002e.109 disabled
PNP: 002e.209 disabled
PNP: 002e.309 disabled
PNP: 002e.a enabled
PNP: 002e.b enabled
PNP: 002e.c disabled
PNP: 002e.d enabled
PNP: 002e.e disabled
PNP: 002e.f disabled
scan_lpc_bus for PCI: 00:14.3 done
scan_bus: scanning of bus PCI: 00:14.3 took 537 usecs
PCI: 00:14.4 scanning...
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 01
scan_bus: scanning of bus PCI: 00:14.4 took 74 usecs
PCI: 00:15.0 scanning...
do_pci_scan_bridge for PCI: 00:15.0
PCI: pci_scan_bus for bus 02
scan_bus: scanning of bus PCI: 00:15.0 took 61 usecs
PCI: 00:15.1 scanning...
do_pci_scan_bridge for PCI: 00:15.1
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [10ec/8168] enabled
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
ASPM: Enabled L0s and L1
scan_bus: scanning of bus PCI: 00:15.1 took 119 usecs
PCI: 00:15.2 scanning...
do_pci_scan_bridge for PCI: 00:15.2
PCI: pci_scan_bus for bus 04
scan_bus: scanning of bus PCI: 00:15.2 took 62 usecs
scan_bus: scanning of bus DOMAIN: 0000 took 93837 usecs
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 93866 usecs
done
BS: BS_DEV_ENUMERATE times (us): entry 0 run 94077 exit 0
found VGA at PCI: 00:01.0
Setting up VGA for PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
Fam14h - domain_read_resources
DOMAIN: 0000 read_resources bus 0 link: 0
Fam14h - nb_read_resources
Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000.
PCI: 00:14.0 read_resources bus 0 link: 0
I2C: 00:50 missing read_resources
I2C: 00:51 missing read_resources
PCI: 00:14.0 read_resources bus 0 link: 0 done
SB800 - Lpc.c - lpc_read_resources - Start.
SB800 - Lpc.c - lpc_read_resources - End.
PCI: 00:14.3 read_resources bus 0 link: 0
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 1 link: 0
PCI: 00:14.4 read_resources bus 1 link: 0 done
PCI: 00:15.0 read_resources bus 2 link: 0
PCI: 00:15.0 read_resources bus 2 link: 0 done
PCI: 00:15.1 read_resources bus 3 link: 0
PCI: 00:15.1 read_resources bus 3 link: 0 done
PCI: 00:15.2 register 10(ffffffff), read-only ignoring it
PCI: 00:15.2 register 14(ffffffff), read-only ignoring it
PCI: 00:15.2 register 38(ffffffff), read-only ignoring it
PCI: 00:15.2 read_resources bus 4 link: 0
PCI: 00:15.2 read_resources bus 4 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: 01
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:00.0
PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
PCI: 00:01.0
PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10
PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 18
PCI: 00:01.1
PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
PCI: 00:04.0
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:11.0
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:12.2
PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:13.2
PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 00:14.0 child on link 0 I2C: 00:50
I2C: 00:50
I2C: 00:51
PCI: 00:14.1
PCI: 00:14.2
PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.1
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
PNP: 002e.6
PNP: 002e.6 resource base 100 size 8 align 3 gran 3 limit fff flags c0000100 index 60
PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.107
PNP: 002e.207
PNP: 002e.307
PNP: 002e.307 resource base 28 size 0 align 0 gran 0 limit 0 flags c0000400 index 23
PNP: 002e.307 resource base bf size 0 align 0 gran 0 limit 0 flags c0000400 index e4
PNP: 002e.307 resource base 27 size 0 align 0 gran 0 limit 0 flags c0000400 index ed
PNP: 002e.407
PNP: 002e.8
PNP: 002e.9
PNP: 002e.9 resource base 42 size 0 align 0 gran 0 limit 0 flags c0000400 index 2a
PNP: 002e.9 resource base e3 size 0 align 0 gran 0 limit 0 flags c0000400 index e0
PNP: 002e.109
PNP: 002e.209
PNP: 002e.309
PNP: 002e.a
PNP: 002e.a resource base 10 size 0 align 0 gran 0 limit 0 flags c0000400 index e7
PNP: 002e.b
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags c0000100 index 60
PNP: 002e.b resource base 0 size 2 align 1 gran 1 limit fff flags c0000100 index 62
PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.c
PNP: 002e.d
PNP: 002e.d resource base 90 size 0 align 0 gran 0 limit 0 flags c0000400 index ec
PNP: 002e.e
PNP: 002e.e resource base 0 size 8 align 3 gran 3 limit fff flags c0000100 index 60
PNP: 002e.e resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.f
PCI: 00:14.4
PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:14.5
PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:15.0
PCI: 00:15.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:15.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:15.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:15.1 child on link 0 PCI: 03:00.0
PCI: 00:15.1 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:15.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:15.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
PCI: 00:15.2
PCI: 00:15.3
PCI: 00:16.0
PCI: 00:16.2
PCI: 00:18.0
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.4
PCI: 00:18.5
PCI: 00:18.6
PCI: 00:18.7
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:15.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:15.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:15.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 03:00.0 10 * [0x0 - 0xff] io
PCI: 00:15.1 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:15.1 1c * [0x0 - 0xfff] io
PCI: 00:01.0 14 * [0x1000 - 0x10ff] io
PCI: 00:11.0 20 * [0x1400 - 0x140f] io
PCI: 00:11.0 10 * [0x1410 - 0x1417] io
PCI: 00:11.0 18 * [0x1418 - 0x141f] io
PCI: 00:11.0 14 * [0x1420 - 0x1423] io
PCI: 00:11.0 1c * [0x1424 - 0x1427] io
DOMAIN: 0000 io: base: 1428 size: 1428 align: 12 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:15.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:15.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:15.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:15.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:15.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem
PCI: 03:00.0 18 * [0x4000 - 0x4fff] prefmem
PCI: 00:15.1 prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:15.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:15.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:01.0 10 * [0x0 - 0xfffffff] prefmem
PCI: 00:15.1 24 * [0x10000000 - 0x100fffff] prefmem
PCI: 00:01.0 18 * [0x10100000 - 0x1013ffff] mem
PCI: 00:01.1 10 * [0x10140000 - 0x10143fff] mem
PCI: 00:14.2 10 * [0x10144000 - 0x10147fff] mem
PCI: 00:12.0 10 * [0x10148000 - 0x10148fff] mem
PCI: 00:13.0 10 * [0x10149000 - 0x10149fff] mem
PCI: 00:14.5 10 * [0x1014a000 - 0x1014afff] mem
PCI: 00:11.0 24 * [0x1014b000 - 0x1014b3ff] mem
PCI: 00:12.2 10 * [0x1014c000 - 0x1014c0ff] mem
PCI: 00:13.2 10 * [0x1014d000 - 0x1014d0ff] mem
DOMAIN: 0000 mem: base: 1014d100 size: 1014d100 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed)
constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
skipping PNP: 002e.307@23 fixed resource, size=0!
skipping PNP: 002e.307@e4 fixed resource, size=0!
skipping PNP: 002e.307@ed fixed resource, size=0!
skipping PNP: 002e.9@2a fixed resource, size=0!
skipping PNP: 002e.9@e0 fixed resource, size=0!
skipping PNP: 002e.a@e7 fixed resource, size=0!
skipping PNP: 002e.d@ec fixed resource, size=0!
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 base e0000000 limit f7ffffff
Setting resources...
DOMAIN: 0000 io: base:1000 size:1428 align:12 gran:0 limit:ffff
PCI: 00:15.1 1c * [0x1000 - 0x1fff] io
PCI: 00:01.0 14 * [0x2000 - 0x20ff] io
PCI: 00:11.0 20 * [0x2400 - 0x240f] io
PCI: 00:11.0 10 * [0x2410 - 0x2417] io
PCI: 00:11.0 18 * [0x2418 - 0x241f] io
PCI: 00:11.0 14 * [0x2420 - 0x2423] io
PCI: 00:11.0 1c * [0x2424 - 0x2427] io
DOMAIN: 0000 io: next_base: 2428 size: 1428 align: 12 gran: 0 done
PCI: 00:14.4 io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:14.4 io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:15.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:15.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:15.1 io: base:1000 size:1000 align:12 gran:12 limit:1fff
PCI: 03:00.0 10 * [0x1000 - 0x10ff] io
PCI: 00:15.1 io: next_base: 1100 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:e0000000 size:1014d100 align:28 gran:0 limit:f7ffffff
PCI: 00:01.0 10 * [0xe0000000 - 0xefffffff] prefmem
PCI: 00:15.1 24 * [0xf0000000 - 0xf00fffff] prefmem
PCI: 00:01.0 18 * [0xf0100000 - 0xf013ffff] mem
PCI: 00:01.1 10 * [0xf0140000 - 0xf0143fff] mem
PCI: 00:14.2 10 * [0xf0144000 - 0xf0147fff] mem
PCI: 00:12.0 10 * [0xf0148000 - 0xf0148fff] mem
PCI: 00:13.0 10 * [0xf0149000 - 0xf0149fff] mem
PCI: 00:14.5 10 * [0xf014a000 - 0xf014afff] mem
PCI: 00:11.0 24 * [0xf014b000 - 0xf014b3ff] mem
PCI: 00:12.2 10 * [0xf014c000 - 0xf014c0ff] mem
PCI: 00:13.2 10 * [0xf014d000 - 0xf014d0ff] mem
DOMAIN: 0000 mem: next_base: f014d100 size: 1014d100 align: 28 gran: 0 done
PCI: 00:14.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:14.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:14.4 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:14.4 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:15.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:15.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:15.0 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:15.0 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
PCI: 00:15.1 prefmem: base:f0000000 size:100000 align:20 gran:20 limit:f00fffff
PCI: 03:00.0 20 * [0xf0000000 - 0xf0003fff] prefmem
PCI: 03:00.0 18 * [0xf0004000 - 0xf0004fff] prefmem
PCI: 00:15.1 prefmem: next_base: f0005000 size: 100000 align: 20 gran: 20 done
PCI: 00:15.1 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
PCI: 00:15.1 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
Fam14h - domain_set_resources
amsr - incoming dev = 00135040
adsr: (before) basek = 0, limitk = 21effffff.
adsr: (after) basek = 0, limitk = 87bfff, sizek = 87c000.
adsr - 0xa0000 to 0xbffff resource.
adsr: mmio_basek=00380000, basek=00000300, limitk=0087bfff
0: mmio_basek=00380000, basek=00400000, limitk=0087bfff
adsr - mmio_basek = 380000.
DOMAIN: 0000 assign_resources, bus 0 link: 0
Fam14h - nb_set_resources
Fam14h - create_vga_resource
Fam14h - set_resource
PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem
PCI: 00:01.0 14 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 00:01.0 18 <- [0x00f0100000 - 0x00f013ffff] size 0x00040000 gran 0x12 mem
PCI: 00:01.1 10 <- [0x00f0140000 - 0x00f0143fff] size 0x00004000 gran 0x0e mem
PCI: 00:11.0 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran 0x03 io
PCI: 00:11.0 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran 0x02 io
PCI: 00:11.0 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran 0x03 io
PCI: 00:11.0 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran 0x02 io
PCI: 00:11.0 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran 0x04 io
PCI: 00:11.0 24 <- [0x00f014b000 - 0x00f014b3ff] size 0x00000400 gran 0x0a mem
PCI: 00:12.0 10 <- [0x00f0148000 - 0x00f0148fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.2 10 <- [0x00f014c000 - 0x00f014c0ff] size 0x00000100 gran 0x08 mem
PCI: 00:13.0 10 <- [0x00f0149000 - 0x00f0149fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.2 10 <- [0x00f014d000 - 0x00f014d0ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.2 10 <- [0x00f0144000 - 0x00f0147fff] size 0x00004000 gran 0x0e mem64
SB800 - Lpc.c - lpc_set_resources - Start.
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
PNP: 002e.307 23 <- [0x0000000028 - 0x0000000027] size 0x00000000 gran 0x00 irq
PNP: 002e.307 e4 <- [0x00000000bf - 0x00000000be] size 0x00000000 gran 0x00 irq
PNP: 002e.307 ed <- [0x0000000027 - 0x0000000026] size 0x00000000 gran 0x00 irq
PNP: 002e.9 2a <- [0x0000000042 - 0x0000000041] size 0x00000000 gran 0x00 irq
PNP: 002e.9 e0 <- [0x00000000e3 - 0x00000000e2] size 0x00000000 gran 0x00 irq
PNP: 002e.a e7 <- [0x0000000010 - 0x000000000f] size 0x00000000 gran 0x00 irq
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
PNP: 002e.b 62 <- [0x0000000000 - 0x0000000001] size 0x00000002 gran 0x01 io
PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq
PNP: 002e.d ec <- [0x0000000090 - 0x000000008f] size 0x00000000 gran 0x00 irq
PCI: 00:14.3 assign_resources, bus 0 link: 0
SB800 - Lpc.c - lpc_set_resources - End.
PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:14.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:14.4 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 mem
PCI: 00:14.5 10 <- [0x00f014a000 - 0x00f014afff] size 0x00001000 gran 0x0c mem
PCI: 00:15.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:15.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:15.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:15.1 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:15.1 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14 bus 03 prefmem
PCI: 00:15.1 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 mem
PCI: 00:15.1 assign_resources, bus 3 link: 0
PCI: 03:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 03:00.0 18 <- [0x00f0004000 - 0x00f0004fff] size 0x00001000 gran 0x0c prefmem64
PCI: 03:00.0 20 <- [0x00f0000000 - 0x00f0003fff] size 0x00004000 gran 0x0e prefmem64
PCI: 00:15.1 assign_resources, bus 3 link: 0
DOMAIN: 0000 assign_resources, bus 0 link: 0
adsr - leaving this lovely routine.
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: 01
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 1000 size 1428 align 12 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base e0000000 size 1014d100 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
DOMAIN: 0000 resource base c0000 size dff40000 align 0 gran 0 limit 0 flags e0004200 index 20
DOMAIN: 0000 resource base 100000000 size 11efffc00 align 0 gran 0 limit 0 flags e0004200 index 30
DOMAIN: 0000 resource base c8000000 size 18000000 align 0 gran 0 limit 0 flags f0000200 index 7
PCI: 00:00.0
PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
PCI: 00:01.0
PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001200 index 10
PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 14
PCI: 00:01.0 resource base f0100000 size 40000 align 18 gran 18 limit f013ffff flags 60000200 index 18
PCI: 00:01.1
PCI: 00:01.1 resource base f0140000 size 4000 align 14 gran 14 limit f0143fff flags 60000200 index 10
PCI: 00:04.0
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:11.0
PCI: 00:11.0 resource base 2410 size 8 align 3 gran 3 limit 2417 flags 60000100 index 10
PCI: 00:11.0 resource base 2420 size 4 align 2 gran 2 limit 2423 flags 60000100 index 14
PCI: 00:11.0 resource base 2418 size 8 align 3 gran 3 limit 241f flags 60000100 index 18
PCI: 00:11.0 resource base 2424 size 4 align 2 gran 2 limit 2427 flags 60000100 index 1c
PCI: 00:11.0 resource base 2400 size 10 align 4 gran 4 limit 240f flags 60000100 index 20
PCI: 00:11.0 resource base f014b000 size 400 align 12 gran 10 limit f014b3ff flags 60000200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base f0148000 size 1000 align 12 gran 12 limit f0148fff flags 60000200 index 10
PCI: 00:12.2
PCI: 00:12.2 resource base f014c000 size 100 align 12 gran 8 limit f014c0ff flags 60000200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base f0149000 size 1000 align 12 gran 12 limit f0149fff flags 60000200 index 10
PCI: 00:13.2
PCI: 00:13.2 resource base f014d000 size 100 align 12 gran 8 limit f014d0ff flags 60000200 index 10
PCI: 00:14.0 child on link 0 I2C: 00:50
I2C: 00:50
I2C: 00:51
PCI: 00:14.1
PCI: 00:14.2
PCI: 00:14.2 resource base f0144000 size 4000 align 14 gran 14 limit f0147fff flags 60000201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.1
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
PNP: 002e.6
PNP: 002e.6 resource base 100 size 8 align 3 gran 3 limit fff flags c0000100 index 60
PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.107
PNP: 002e.207
PNP: 002e.307
PNP: 002e.307 resource base 28 size 0 align 0 gran 0 limit 0 flags e0000400 index 23
PNP: 002e.307 resource base bf size 0 align 0 gran 0 limit 0 flags e0000400 index e4
PNP: 002e.307 resource base 27 size 0 align 0 gran 0 limit 0 flags e0000400 index ed
PNP: 002e.407
PNP: 002e.8
PNP: 002e.9
PNP: 002e.9 resource base 42 size 0 align 0 gran 0 limit 0 flags e0000400 index 2a
PNP: 002e.9 resource base e3 size 0 align 0 gran 0 limit 0 flags e0000400 index e0
PNP: 002e.109
PNP: 002e.209
PNP: 002e.309
PNP: 002e.a
PNP: 002e.a resource base 10 size 0 align 0 gran 0 limit 0 flags e0000400 index e7
PNP: 002e.b
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags e0000100 index 60
PNP: 002e.b resource base 0 size 2 align 1 gran 1 limit fff flags e0000100 index 62
PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.c
PNP: 002e.d
PNP: 002e.d resource base 90 size 0 align 0 gran 0 limit 0 flags e0000400 index ec
PNP: 002e.e
PNP: 002e.e resource base 0 size 8 align 3 gran 3 limit fff flags c0000100 index 60
PNP: 002e.e resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.f
PCI: 00:14.4
PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:14.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
PCI: 00:14.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20
PCI: 00:14.5
PCI: 00:14.5 resource base f014a000 size 1000 align 12 gran 12 limit f014afff flags 60000200 index 10
PCI: 00:15.0
PCI: 00:15.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:15.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
PCI: 00:15.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20
PCI: 00:15.1 child on link 0 PCI: 03:00.0
PCI: 00:15.1 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
PCI: 00:15.1 resource base f0000000 size 100000 align 20 gran 20 limit f00fffff flags 60081202 index 24
PCI: 00:15.1 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 10
PCI: 03:00.0 resource base f0004000 size 1000 align 12 gran 12 limit f0004fff flags 60001201 index 18
PCI: 03:00.0 resource base f0000000 size 4000 align 14 gran 14 limit f0003fff flags 60001201 index 20
PCI: 00:15.2
PCI: 00:15.3
PCI: 00:16.0
PCI: 00:16.2
PCI: 00:18.0
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.4
PCI: 00:18.5
PCI: 00:18.6
PCI: 00:18.7
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 3378 exit 0
Warning: Can't write PCI_INTR 0xC00/0xC01 registers because
'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL
Warning: Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist
Enabling resources...
Fam14h - domain_enable_resources
AmdInitMid: Start
DispatchCpuFeatures: MidStart
DispatchCpuFeatures: MidEnd
GfxInitAtMidPost Enter
S3 Save: PCI WR Address: 0x000c10bc Data: 0x00000000
S3 Save: PCI WR Address: 0x000c10b8 Data: 0x00000000
S3 Save: PCI WR Address: 0x000c10b4 Data: 0x00000000
S3 Save: PCI WR Address: 0x000c10b0 Data: 0x00000000
S3 Save: PCI WR Address: 0x000c10ac Data: 0x00000000
S3 Save: PCI WR Address: 0x000c10a8 Data: 0x00000000
S3 Save: PCI WR Address: 0x000c10a4 Data: 0x00000000
S3 Save: PCI WR Address: 0x000c10a0 Data: 0x00000000
S3 Save: PCI WR Address: 0x000c109c Data: 0x00000000
S3 Save: PCI WR Address: 0x000c1098 Data: 0x00000000
S3 Save: PCI WR Address: 0x000c1094 Data: 0x00000000
S3 Save: PCI WR Address: 0x000c1090 Data: 0x00000000
S3 Save: PCI WR Address: 0x000c108c Data: 0x00fecf00
S3 Save: PCI WR Address: 0x000c1088 Data: 0x00e00003
S3 Save: PCI WR Address: 0x000c1084 Data: 0x00fedf80
S3 Save: PCI WR Address: 0x000c1080 Data: 0x00fed003
S3 Save: PCI WR Address: 0x00008024 Data: 0x00000000
S3 Save: PCI WR Address: 0x00008020 Data: 0x00000000
S3 Save: PCI WR Address: 0x0000801c Data: 0x00000000
S3 Save: PCI WR Address: 0x00008018 Data: 0xf0100000
S3 Save: PCI WR Address: 0x00008014 Data: 0x00002001
S3 Save: PCI WR Address: 0x00008010 Data: 0xe0000008
S3 Save: PCI WR Address: 0x00008004 Data: 0x0006
GfxGmcInit Enter
S3 Save: MEM WR Address: 0xf01020c0 Data: 0x00000c80
S3 Save: MEM WR Address: 0xf01020b8 Data: 0x00000400
S3 Save: MEM WR Address: 0xf01020bc Data: 0x00000400
S3 Save: MEM WR Address: 0xf0102640 Data: 0x00000400
S3 Save: MEM WR Address: 0xf010263c Data: 0x00000400
S3 Save: MEM WR Address: 0xf0102638 Data: 0x00000400
S3 Save: MEM WR Address: 0xf01015c0 Data: 0x00081401
S3 Save: MEM WR Address: 0xf010281c Data: 0x00000001
S3 Save: MEM WR Address: 0xf0102824 Data: 0x00000109
S3 Save: MEM WR Address: 0xf010282c Data: 0x00000201
S3 Save: MEM WR Address: 0xf0102834 Data: 0x00000309
S3 Save: MEM WR Address: 0xf010283c Data: 0x01f83ce0
S3 Save: MEM WR Address: 0xf0102840 Data: 0x01f83ce0
S3 Save: MEM WR Address: 0xf010284c Data: 0x00020077
S3 Save: MEM WR Address: 0xf010284c Data: 0x00030077
S3 Save: MEM WR Address: 0xf010284c Data: 0x00030077
S3 Save: MEM WR Address: 0xf0102854 Data: 0x00000100
S3 Save: MEM WR Address: 0xf0102858 Data: 0x00000200
S3 Save: MEM WR Address: 0xf010285c Data: 0x60002001
S3 Save: MEM WR Address: 0xf010277c Data: 0x0e0e0808
S3 Save: MEM WR Address: 0xf01028d8 Data: 0x0e0e0808
S3 Save: MEM WR Address: 0xf0102780 Data: 0x0a110715
S3 Save: MEM WR Address: 0xf01028dc Data: 0x0a110715
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x00000000
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x001e0a07
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x00000020
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00050500
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x00000027
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x0001050c
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x0000002a
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x0001051c
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x0000002d
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00030534
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x00000032
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x0001053e
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x00000035
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00010546
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x00000038
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x0002054e
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x0000003c
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00010557
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x0000003f
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x0001055f
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x00000042
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00010567
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x00000045
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x0001056f
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x00000048
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00050572
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x0000004f
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00000800
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x00000051
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00260801
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x00000079
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x004b082d
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x000000c6
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x0013088d
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x000000db
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x100008a1
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00000040
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00000040
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x000000df
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x000008a2
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x000000e1
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x0001094d
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x000000e4
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00000952
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x000000e6
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00010954
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x000000e9
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x0009095a
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x000000f4
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x0022096e
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x00000118
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x000e0997
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x00000128
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x100009a6
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00000040
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00000040
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x0000012c
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x000009a7
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x0000012e
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x002e09d7
S3 Save: MEM WR Address: 0xf0102b8c Data: 0x0000015e
S3 Save: MEM WR Address: 0xf0102b90 Data: 0x00170a26
S3 Save: MEM WR Address: 0xf0102b94 Data: 0x5d976000
S3 Save: MEM WR Address: 0xf0102b98 Data: 0x410af020
S3 Save: MEM WR Address: 0xf0102024 Data: 0x0f170f00
S3 Save: MEM WR Address: 0xf0102898 Data: 0x0f000c80
S3 Save: MEM WR Address: 0xf0102c04 Data: 0x0f000000
S3 Save: MEM WR Address: 0xf0105428 Data: 0x18000000
S3 Save: MEM WR Address: 0xf0105490 Data: 0x00000001
S3 Save: MEM WR Address: 0xf0105490 Data: 0x00000003
S3 Save: MEM WR Address: 0xf010286c Data: 0x00000c80
S3 Save: MEM WR Address: 0xf010287c Data: 0x00000dff
S3 Save: MEM WR Address: 0xf0102894 Data: 0x000dfffb
S3 Save: MEM WR Address: 0xf0102870 Data: 0x000fffff
S3 Save: MEM WR Address: 0xf0102874 Data: 0x000fffff
S3 Save: MEM WR Address: 0xf0102878 Data: 0x000fffff
S3 Save: MEM WR Address: 0xf010288c Data: 0x000021f0
S3 Save: MEM WR Address: 0xf0102890 Data: 0x000021ff
S3 Save: MEM WR Address: 0xf0102864 Data: 0x32100876
S3 Save: MEM WR Address: 0xf0102b98 Data: 0x490af020
S3 Save: MEM WR Address: 0xf01027cc Data: 0x00032005
S3 Save: MEM WR Address: 0xf01027dc Data: 0x00734847
S3 Save: MEM WR Address: 0xf01027d0 Data: 0x00012008
S3 Save: MEM WR Address: 0xf01027e0 Data: 0x00003d3c
S3 Save: MEM WR Address: 0xf0102784 Data: 0x00000007
S3 Save: MEM WR Address: 0xf01021c8 Data: 0x0000a1f1
S3 Save: MEM WR Address: 0xf010217c Data: 0x0000a1f1
S3 Save: MEM WR Address: 0xf0102188 Data: 0x000221b1
S3 Save: MEM WR Address: 0xf0102814 Data: 0x00000200
S3 Save: MEM WR Address: 0xf010201c Data: 0x03330003
S3 Save: MEM WR Address: 0xf0102020 Data: 0x70760007
S3 Save: MEM WR Address: 0xf0102018 Data: 0x00000050
S3 Save: MEM WR Address: 0xf0102014 Data: 0x00005500
S3 Save: MEM WR Address: 0xf0102610 Data: 0x44111222
S3 Save: MEM WR Address: 0xf0102618 Data: 0x00006664
S3 Save: MEM WR Address: 0xf0102614 Data: 0x11333111
S3 Save: MEM WR Address: 0xf010261c Data: 0x00000003
S3 Save: MEM WR Address: 0xf010279c Data: 0xfcfcfdfc
S3 Save: MEM WR Address: 0xf01027a0 Data: 0xfcfcfdfc
S3 Save: MEM WR Address: 0xf01025c8 Data: 0x007f605f
S3 Save: MEM WR Address: 0xf01025cc Data: 0x00007f7e
S3 Save: MEM WR Address: 0xf01020b4 Data: 0x00000000
S3 Save: MEM WR Address: 0xf01028c8 Data: 0x00000003
S3 Save: MEM WR Address: 0xf010202c Data: 0x0003ffff
S3 Save: MEM WR Address: 0xf01025c0 Data: 0x00000000
S3 Save: MEM WR Address: 0xf01020ec Data: 0x000001fc
S3 Save: MEM WR Address: 0xf01020d4 Data: 0x00000016
S3 Save: MEM WR Address: 0xf01020c0 Data: 0x00040c80
S3 Save: MEM WR Address: 0xf01020b8 Data: 0x00040400
S3 Save: MEM WR Address: 0xf01020bc Data: 0x00040400
S3 Save: MEM WR Address: 0xf0102640 Data: 0x00040400
S3 Save: MEM WR Address: 0xf010263c Data: 0x00040400
S3 Save: MEM WR Address: 0xf0102638 Data: 0x00040400
S3 Save: MEM WR Address: 0xf01015c0 Data: 0x000c1401
S3 Save: MEM WR Address: 0xf0102b94 Data: 0x5d976001
S3 Save: MEM WR Address: 0xf0102b98 Data: 0x490af820
GfxGmcInit Exit
GfxSetBootUpVoltage Enter
S3 Save: MEM WR Address: 0xf0100770 Data: 0x0000000e
S3 Save: MEM WR Address: 0xf0100770 Data: 0x0000000b
GfxSetBootUpVoltage Exit
S3 Save: PCI WR Address: 0x0000804c Data: 0x98021002
S3 Save: PCI WR Address: 0x0000904c Data: 0x13141002
GfxInitAtMidPost Exit [0x0]
GfxIntegratedInfoTableEntry Enter
GfxIntegratedInfoTableInit Enter
GfxIntegratedEnumerateAllConnectors Enter
Allocate Display Connector at Primary sPath[0]
usDeviceConnector = 0x3113
usDeviceTag = 0x8
usDeviceACPIEnum = 0x210
usExtEncoderObjId = 0x0
ucChannelMapping = 0xe4
Allocate Display Connector at Primary sPath[1]
usDeviceConnector = 0x3213
usDeviceTag = 0x80
usDeviceACPIEnum = 0x220
usExtEncoderObjId = 0x0
ucChannelMapping = 0xe4
GfxIntegratedEnumerateAllConnectors Exit [0x0]
< --- Power Play Table ------ >
Table Revision = 1
State #1
Classification 0x4000
VCLK = 40000kHz
DCLK = 30477kHz
DPM State Index: 0
State #2
Classification 0x400
VCLK = 53334kHz
DCLK = 40000kHz
DPM State Index: 1
State #3
Classification 0x1
VCLK = 0kHz
DCLK = 0kHz
DPM State Index: 0
State #4
Classification 0x5
VCLK = 0kHz
DCLK = 0kHz
DPM State Index: 0 2
State #5
Classification 0x8
VCLK = 0kHz
DCLK = 0kHz
DPM State Index: 3
State #6
Classification 0x10
VCLK = 0kHz
DCLK = 0kHz
DPM State Index: 4
DPM State #0
SCLK = 27827
VID index = 0
tdpLimit = 0
DPM State #1
SCLK = 49231
VID index = 2
tdpLimit = 0
DPM State #2
SCLK = 49231
VID index = 1
tdpLimit = 0
DPM State #3
SCLK = 20000
VID index = 0
tdpLimit = 0
DPM State #4
SCLK = 17778
VID index = 0
tdpLimit = 0
ulSB_MMIO_Base_Addr = 0xfed80000
GfxIntegratedInfoTableInit Exit [0x0]
GfxIntegratedInfoTableEntry Exit[0x0]
PcieInitAtMid Enter
S3 Save: PCI WR Address: 0x00000060 Data: 0x0000008c
S3 Save: PCI WR Address: 0x00000064 Data: 0x00000000
S3 Save: PCI WR Address: 0x00000060 Data: 0x00000080
S3 Save: PCI WR Address: 0x00000064 Data: 0x00000042
*WR PCIEIND_P (0:4:0):0x00a2 = 0x00601436
S3 Save: PCI WR Address: 0x000200e0 Data: 0x000200a2
S3 Save: PCI WR Address: 0x000200e4 Data: 0x00601436
*WR PCIEIND_P (0:4:0):0x00c0 = 0x00008000
S3 Save: PCI WR Address: 0x000200e0 Data: 0x000200c0
S3 Save: PCI WR Address: 0x000200e4 Data: 0x00008000
PcieAspmCallback for Device = 0:4:0
S3 Save: PCI WR Address: 0x00020018 Data: 0x00000000
*WR PCIEIND_P (0:8:0):0x00a2 = 0x00701636
S3 Save: PCI WR Address: 0x000400e0 Data: 0x000200a2
S3 Save: PCI WR Address: 0x000400e4 Data: 0x00701636
*WR PCIEIND_P (0:8:0):0x00c0 = 0x00008000
S3 Save: PCI WR Address: 0x000400e0 Data: 0x000200c0
S3 Save: PCI WR Address: 0x000400e4 Data: 0x00008000
S3 Save: PCI WR Address: 0x0004006c Data: 0x00442580
S3 Save: IO WR Address: 0x00000cd8 Data: 0x40000038
S3 Save: IO WR Address: 0x00000cdc Data: 0x000000a0
S3 Save: IO WR Address: 0x00000cd8 Data: 0x4000003c
S3 Save: IO WR Address: 0x00000cdc Data: 0x60006930
S3 Save: IO WR Address: 0x00000cd8 Data: 0x80000068
S3 Save: IO WR Address: 0x00000cdc Data: 0x10410003
S3 Save: PCI WR Address: 0x00040068 Data: 0x03
PcieFmSetBootUpVoltage Enter
*WR SMUx0B:0x8600 = 0x18650a2
*WR SMUx0B:0x8604 = 0x7000fe04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
Set Voltage for Gen 2, Vid Index 3
S3 Save: PCI WR Address: 0x00000060 Data: 0x000000ea
S3 Save: PCI WR Address: 0x00000060 Data: 0x000000ea
S3 Save: PCI WR Address: 0x00000064 Data: 0x0000001e
S3 Save: PCI WR Address: 0x00000060 Data: 0x000000ea
S3 Save: PCI WR Address: 0x00000064 Data: 0x00000012
S3 Save: PCI WR Address: 0x00000060 Data: 0x000000eb
S3 Save: PCI WR Address: 0x00000060 Data: 0x000000ea
S3 Save: PCI WR Address: 0x00000060 Data: 0x000000ea
S3 Save: PCI WR Address: 0x00000064 Data: 0x00000012
S3 Save: PCI WR Address: 0x00000060 Data: 0x000000ea
S3 Save: PCI WR Address: 0x00000064 Data: 0x0000001e
S3 Save: PCI WR Address: 0x00000060 Data: 0x000000eb
PcieFmSetBootUpVoltage Exit
PcieLateInit Enter
PciePwrPowerDownUnusedLanes Enter
*WR GPP WRAP (0:0:0):0x01308023 = 0x0000000f
S3 Save: PCI WR Address: 0x000000e0 Data: 0x01308023
S3 Save: PCI WR Address: 0x000000e4 Data: 0x0000000f
PciePifPllPowerDown Enter
*WR GPP PIF0 (0:0:0):0x01100013 = 0x00011ff7
S3 Save: PCI WR Address: 0x000000e0 Data: 0x01100013
S3 Save: PCI WR Address: 0x000000e4 Data: 0x00011ff7
PciePifPllPowerDown Exit
PciePwrPowerDownUnusedLanes Exit
PciePwrPowerDownPllInL1 Enter
PcieLanesToPowerDownPllInL1 Enter
Engine 4 Active Lanes 0x0, Hotplug Lanes 0x0
Engine 5 Active Lanes 0x0, Hotplug Lanes 0x0
Engine 6 Active Lanes 0x0, Hotplug Lanes 0x0
Engine 7 Active Lanes 0x0, Hotplug Lanes 0x0
Engine 8 Active Lanes 0xf, Hotplug Lanes 0x0
Index 0 Final Latency 255
Index 1 Final Latency 255
Index 2 Final Latency 255
Index 3 Final Latency 255
Lane bitmap ffff
PcieLanesToPowerDownPllInL1 Exit
*WR GPP PIF0 (0:0:0):0x01100012 = 0x01011fa2
S3 Save: PCI WR Address: 0x000000e0 Data: 0x01100012
S3 Save: PCI WR Address: 0x000000e4 Data: 0x01011fa2
*WR GPP PIF0 (0:0:0):0x01100013 = 0x01011fa2
S3 Save: PCI WR Address: 0x000000e0 Data: 0x01100013
S3 Save: PCI WR Address: 0x000000e4 Data: 0x01011fa2
PciePwrPowerDownPllInL1 Exir
PciePwrClockGating Enter
*WR GPP WRAP (0:0:0):0x01308014 = 0xfff11003
S3 Save: PCI WR Address: 0x000000e0 Data: 0x01308014
S3 Save: PCI WR Address: 0x000000e4 Data: 0xfff11003
*WR GPP WRAP (0:0:0):0x01308012 = 0x07810781
S3 Save: PCI WR Address: 0x000000e0 Data: 0x01308012
S3 Save: PCI WR Address: 0x000000e4 Data: 0x07810781
*WR GPP WRAP (0:0:0):0x01308011 = 0x817ffeff
S3 Save: PCI WR Address: 0x000000e0 Data: 0x01308011
S3 Save: PCI WR Address: 0x000000e4 Data: 0x817ffeff
*WR GPP CORE (0:0:0):0x01010011 = 0x0000000f
S3 Save: PCI WR Address: 0x000000e0 Data: 0x01010011
S3 Save: PCI WR Address: 0x000000e4 Data: 0x0000000f
*WR GPP WRAP (0:0:0):0x01308016 = 0x00ff0000
S3 Save: PCI WR Address: 0x000000e0 Data: 0x01308016
S3 Save: PCI WR Address: 0x000000e4 Data: 0x00ff0000
PciePwrClockGating Exit
PcieLockRegisters Enter
*WR GPP CORE (0:0:0):0x01010010 = 0x80631201
S3 Save: PCI WR Address: 0x000000e0 Data: 0x01010010
S3 Save: PCI WR Address: 0x000000e4 Data: 0x80631201
PcieLockRegisters Exit
PcieLateInit Exit [0x0]
S3 Save: PCI WR Address: 0x00000060 Data: 0x0000008c
S3 Save: PCI WR Address: 0x00000064 Data: 0x000000f0
S3 Save: PCI WR Address: 0x00000060 Data: 0x00000080
S3 Save: PCI WR Address: 0x00000064 Data: 0x00000002
PcieInitAtMid Exit [0x0]
NbInitAtLatePost Enter
NbInitLclkDeepSleep Enter
LCLK Deep Sleep [Enabled]
S3 Save: DISPATCH Function Id: 0x03, Context: 0x1b, 0x82, 0x00, 0x00, 0x00, 0x05, 0xff, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x1d, 0x82, 0x00, 0x00, 0x00, 0x0f, 0x10, 0x00, 0x00
NbInitLclkDeepSleep Exit
NbInitClockGating Enter
S3 Save: DISPATCH Function Id: 0x03, Context: 0x6f, 0x83, 0x00, 0x00, 0x00, 0xf0, 0x01, 0x60, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x71, 0x83, 0x00, 0x00, 0x00, 0xf0, 0x01, 0x70, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x73, 0x82, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00
S3 Save: PCI WR Address: 0x00000094 Data: 0x00000149
S3 Save: PCI WR Address: 0x00000098 Data: 0x003f8100
S3 Save: PCI WR Address: 0x00000094 Data: 0x0000014a
S3 Save: PCI WR Address: 0x00000098 Data: 0x003f8100
S3 Save: PCI WR Address: 0x00000094 Data: 0x0000014b
S3 Save: PCI WR Address: 0x00000098 Data: 0x00200100
*WR SMUx0B:0x8600 = 0x18650f5
*WR SMUx0B:0x8604 = 0x130ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SRBM (GMM):0xff3001f5 = 0xffffcfff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x00, 0x86, 0x11, 0x00
*WR SMUx0B:0x8600 = 0x18650f5
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xf5, 0x50, 0x86, 0x01
*WR SMUx0B:0x8604 = 0x130ff04
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x04, 0xff, 0x30, 0x01
*WR SMUx0B:0x8608 = 0xc0010000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x50, 0x86, 0x11, 0x00
*WR SMUx0B:0x8650 = 0xffffcfff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xff, 0xcf, 0xff, 0xff
NbSmuServiceRequest Enter [0x0b]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x0b
NbSmuServiceRequest Exit
S3 Save: PCI WR Address: 0x00000060 Data: 0x000000a2
S3 Save: PCI WR Address: 0x00000064 Data: 0x033f8100
S3 Save: PCI WR Address: 0x00000060 Data: 0x000000a3
S3 Save: PCI WR Address: 0x00000064 Data: 0x073f8100
S3 Save: PCI WR Address: 0x00000060 Data: 0x000000a4
S3 Save: PCI WR Address: 0x00000064 Data: 0x183c0100
*WR SMUx0B:0x8600 = 0x18650f5
*WR SMUx0B:0x8604 = 0x130ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SRBM (GMM):0xff3001f5 = 0xffff0fff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x00, 0x86, 0x11, 0x00
*WR SMUx0B:0x8600 = 0x18650f5
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xf5, 0x50, 0x86, 0x01
*WR SMUx0B:0x8604 = 0x130ff04
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x04, 0xff, 0x30, 0x01
*WR SMUx0B:0x8608 = 0xc0010000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x50, 0x86, 0x11, 0x00
*WR SMUx0B:0x8650 = 0xffff0fff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xff, 0x0f, 0xff, 0xff
NbSmuServiceRequest Enter [0x0b]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x0b
NbSmuServiceRequest Exit
*WR SMUx0B:0x8600 = 0x18650f4
*WR SMUx0B:0x8604 = 0x130ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SRBM (GMM):0xff3001f4 = 0xffbfffff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x00, 0x86, 0x11, 0x00
*WR SMUx0B:0x8600 = 0x18650f4
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xf4, 0x50, 0x86, 0x01
*WR SMUx0B:0x8604 = 0x130ff04
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x04, 0xff, 0x30, 0x01
*WR SMUx0B:0x8608 = 0xc0010000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x50, 0x86, 0x11, 0x00
*WR SMUx0B:0x8650 = 0xffbfffff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xff, 0xff, 0xbf, 0xff
NbSmuServiceRequest Enter [0x0b]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x0b
NbSmuServiceRequest Exit
*WR SMUx0B:0x8600 = 0x1865012
*WR SMUx0B:0x8604 = 0x1530ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SRBM (GMM):0xff301512 = 0x40600100
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x00, 0x86, 0x11, 0x00
*WR SMUx0B:0x8600 = 0x1865012
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x12, 0x50, 0x86, 0x01
*WR SMUx0B:0x8604 = 0x1530ff04
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x04, 0xff, 0x30, 0x15
*WR SMUx0B:0x8608 = 0xc0010000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x50, 0x86, 0x11, 0x00
*WR SMUx0B:0x8650 = 0x40600100
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x01, 0x60, 0x40
NbSmuServiceRequest Enter [0x0b]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x0b
NbSmuServiceRequest Exit
*WR SMUx0B:0x8600 = 0x18650f4
*WR SMUx0B:0x8604 = 0x130ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SRBM (GMM):0xff3001f4 = 0xe7bfffff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x00, 0x86, 0x11, 0x00
*WR SMUx0B:0x8600 = 0x18650f4
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xf4, 0x50, 0x86, 0x01
*WR SMUx0B:0x8604 = 0x130ff04
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x04, 0xff, 0x30, 0x01
*WR SMUx0B:0x8608 = 0xc0010000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x50, 0x86, 0x11, 0x00
*WR SMUx0B:0x8650 = 0xe7bfffff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xff, 0xff, 0xbf, 0xe7
NbSmuServiceRequest Enter [0x0b]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x0b
NbSmuServiceRequest Exit
*WR SMUx0B:0x8600 = 0x18650f5
*WR SMUx0B:0x8604 = 0x130ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SRBM (GMM):0xff3001f5 = 0xffff07ff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x00, 0x86, 0x11, 0x00
*WR SMUx0B:0x8600 = 0x18650f5
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xf5, 0x50, 0x86, 0x01
*WR SMUx0B:0x8604 = 0x130ff04
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x04, 0xff, 0x30, 0x01
*WR SMUx0B:0x8608 = 0xc0010000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x50, 0x86, 0x11, 0x00
*WR SMUx0B:0x8650 = 0xffff07ff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xff, 0x07, 0xff, 0xff
NbSmuServiceRequest Enter [0x0b]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x0b
NbSmuServiceRequest Exit
*WR SMUx0B:0x8600 = 0x1865034
*WR SMUx0B:0x8604 = 0x130ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SRBM (GMM):0xff300134 = 0x113c71
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x00, 0x86, 0x11, 0x00
*WR SMUx0B:0x8600 = 0x1865034
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x34, 0x50, 0x86, 0x01
*WR SMUx0B:0x8604 = 0x130ff04
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x04, 0xff, 0x30, 0x01
*WR SMUx0B:0x8608 = 0xc0010000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x50, 0x86, 0x11, 0x00
*WR SMUx0B:0x8650 = 0x113c71
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x71, 0x3c, 0x11, 0x00
NbSmuServiceRequest Enter [0x0b]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x0b
NbSmuServiceRequest Exit
*WR SMUx0B:0x8600 = 0x18650f4
*WR SMUx0B:0x8604 = 0x130ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SRBM (GMM):0xff3001f4 = 0xe5bfffff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x00, 0x86, 0x11, 0x00
*WR SMUx0B:0x8600 = 0x18650f4
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xf4, 0x50, 0x86, 0x01
*WR SMUx0B:0x8604 = 0x130ff04
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x04, 0xff, 0x30, 0x01
*WR SMUx0B:0x8608 = 0xc0010000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x50, 0x86, 0x11, 0x00
*WR SMUx0B:0x8650 = 0xe5bfffff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xff, 0xff, 0xbf, 0xe5
NbSmuServiceRequest Enter [0x0b]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x0b
NbSmuServiceRequest Exit
*WR SMUx0B:0x8600 = 0x1865034
*WR SMUx0B:0x8604 = 0x130ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SRBM (GMM):0xff300134 = 0x113c70
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x00, 0x86, 0x11, 0x00
*WR SMUx0B:0x8600 = 0x1865034
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x34, 0x50, 0x86, 0x01
*WR SMUx0B:0x8604 = 0x130ff04
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x04, 0xff, 0x30, 0x01
*WR SMUx0B:0x8608 = 0xc0010000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x50, 0x86, 0x11, 0x00
*WR SMUx0B:0x8650 = 0x113c70
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x70, 0x3c, 0x11, 0x00
NbSmuServiceRequest Enter [0x0b]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x0b
NbSmuServiceRequest Exit
*WR SMUx0B:0x8600 = 0x186507c
*WR SMUx0B:0x8604 = 0x1b30ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SRBM (GMM):0xff301b7c = 0x6260
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x00, 0x86, 0x11, 0x00
*WR SMUx0B:0x8600 = 0x186507c
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x7c, 0x50, 0x86, 0x01
*WR SMUx0B:0x8604 = 0x1b30ff04
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x04, 0xff, 0x30, 0x1b
*WR SMUx0B:0x8608 = 0xc0010000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x50, 0x86, 0x11, 0x00
*WR SMUx0B:0x8650 = 0x6260
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x60, 0x62, 0x00, 0x00
NbSmuServiceRequest Enter [0x0b]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x0b
NbSmuServiceRequest Exit
*WR SMUx0B:0x8600 = 0x186507c
*WR SMUx0B:0x8604 = 0x1e30ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SRBM (GMM):0xff301e7c = 0x6260
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x00, 0x86, 0x11, 0x00
*WR SMUx0B:0x8600 = 0x186507c
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x7c, 0x50, 0x86, 0x01
*WR SMUx0B:0x8604 = 0x1e30ff04
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x04, 0xff, 0x30, 0x1e
*WR SMUx0B:0x8608 = 0xc0010000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x50, 0x86, 0x11, 0x00
*WR SMUx0B:0x8650 = 0x6260
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x60, 0x62, 0x00, 0x00
NbSmuServiceRequest Enter [0x0b]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x0b
NbSmuServiceRequest Exit
*WR SMUx0B:0x8600 = 0x18650f5
*WR SMUx0B:0x8604 = 0x130ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SRBM (GMM):0xff3001f5 = 0xefff07ff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x00, 0x86, 0x11, 0x00
*WR SMUx0B:0x8600 = 0x18650f5
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xf5, 0x50, 0x86, 0x01
*WR SMUx0B:0x8604 = 0x130ff04
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x04, 0xff, 0x30, 0x01
*WR SMUx0B:0x8608 = 0xc0010000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x50, 0x86, 0x11, 0x00
*WR SMUx0B:0x8650 = 0xefff07ff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xff, 0x07, 0xff, 0xef
NbSmuServiceRequest Enter [0x0b]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x0b
NbSmuServiceRequest Exit
*WR SMUx0B:0x8600 = 0x18650f4
*WR SMUx0B:0x8604 = 0x130ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SMUx0B:0x8600 = 0x18650f5
*WR SMUx0B:0x8604 = 0x130ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SMUx0B:0x8600 = 0x1865012
*WR SMUx0B:0x8604 = 0x1530ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
Clock Gating FCRxFF30_01F4 - 0xe5bfffff
Clock Gating FCRxFF30_01F5 - 0xefff07ff
Clock Gating FCRxFF30_1512 - 0x40600100
NbInitClockGating End
S3 Save: PCI WR Address: 0x00000060 Data: 0x00000080
S3 Save: PCI WR Address: 0x00000064 Data: 0x00000082
NbInitAtLatePost Exit[0x0]
F14NbLclkNclkRatioFeature Enter
Offset for Nclk = 533 Lclk = 320
S3 Save: PCI WR Address: 0x000c6110 Data: 0x98a8a011
Offset for Nclk = 533 Lclk = 492
S3 Save: PCI WR Address: 0x000c6114 Data: 0x989aa071
Offset for Nclk = 336 Lclk = 320
S3 Save: PCI WR Address: 0x000c6118 Data: 0xa6a8a072
Offset for Nclk = 336 Lclk = 492
S3 Save: PCI WR Address: 0x000c611c Data: 0xa69aa033
F14NbLclkNclkRatioFeature Exit
NbLclkDpmFeature Enter
NbFmInitLclkDpmRcActivity F14 Enter
Fused State Index:2 LCLK DPM State [7]: LclkScalingDid - 0x1a, ActivityThreshold - 0x40ffff, SamplingPeriod - 0xc350
Fused State Index:1 LCLK DPM State [6]: LclkScalingDid - 0x1a, ActivityThreshold - 0x40ffff, SamplingPeriod - 0xc350
Fused State Index:0 LCLK DPM State [5]: LclkScalingDid - 0x28, ActivityThreshold - 0x100, SamplingPeriod - 0x1388
S3 Save: DISPATCH Function Id: 0x03, Context: 0x33, 0x83, 0x00, 0x00, 0x00, 0xff, 0x33, 0x80, 0x01
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x34, 0x84, 0x00, 0x00
*WR SMUx0B:0x8434 = 0xc3500013
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x13, 0x00, 0x50, 0xc3
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0xac, 0x84, 0x00, 0x00
*WR SMUx0B:0x84ac = 0x0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
*WR SMUx0B:0x84b0 = 0x0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
*WR SMUx0B:0x84b4 = 0x0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
*WR SMUx0B:0x84b8 = 0x0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
ActivityThreshold[4] - 0x0 ActivityThreshold[5] - 0x100 ActivityThreshold[6] - 0x40ffff ActivityThreshold[7] - 0x40ffff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x70, 0x84, 0x00, 0x00
*WR SMUx0B:0x8470 = 0x0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
*WR SMUx0B:0x8474 = 0x100
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00
*WR SMUx0B:0x8478 = 0x40ffff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xff, 0xff, 0x40, 0x00
*WR SMUx0B:0x847c = 0x40ffff
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xff, 0xff, 0x40, 0x00
SamplingPeriod[4] - 0x1388 SamplingPeriod[5] - 0x0 SamplingPeriod[6] - 0xc350 SamplingPeriod[7] - 0xc350
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x40, 0x84, 0x00, 0x00
*WR SMUx0B:0x8440 = 0x1388
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x88, 0x13, 0x00, 0x00
*WR SMUx0B:0x8444 = 0xc350c350
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x50, 0xc3, 0x50, 0xc3
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x8c, 0x84, 0x00, 0x00
*WR SMUx0B:0x848c = 0x281a1a
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x1a, 0x1a, 0x28, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x98, 0x84, 0x00, 0x00
*WR SMUx0B:0x8498 = 0x103
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x90, 0x84, 0x12, 0x00
*WR SMUx0B:0x8490 = 0xa0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xa0, 0x00, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x35, 0x83, 0x00, 0x00, 0x00, 0x24, 0x90, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x37, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x39, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x3b, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x3d, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x3f, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x41, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x43, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x45, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x47, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x49, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x4b, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x4d, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x4f, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
S3 Save: DISPATCH Function Id: 0x03, Context: 0x51, 0x83, 0x00, 0x00, 0x00, 0x22, 0x88, 0x00, 0x00
*WR SMUx0B:0x8600 = 0x18650e4
*WR SMUx0B:0x8604 = 0x130ff04
*WR SMUx0B:0x8608 = 0xc0000000
NbSmuServiceRequest Enter [0x0b]
NbSmuServiceRequest Exit
*WR SRBM (GMM):0xff3001e4 = 0x100000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x00, 0x86, 0x11, 0x00
*WR SMUx0B:0x8600 = 0x18650e4
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0xe4, 0x50, 0x86, 0x01
*WR SMUx0B:0x8604 = 0x130ff04
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x04, 0xff, 0x30, 0x01
*WR SMUx0B:0x8608 = 0xc0010000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0
S3 Save: DISPATCH Function Id: 0x03, Context: 0x0b, 0x82, 0x00, 0x00, 0x00, 0x50, 0x86, 0x11, 0x00
*WR SMUx0B:0x8650 = 0x100000
S3 Save: DISPATCH Function Id: 0x03, Context: 0x05, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00
NbSmuServiceRequest Enter [0x0b]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x0b
NbSmuServiceRequest Exit
NbSmuServiceRequest Enter [0x08]
S3 Save: DISPATCH Function Id: 0x01, Context: 0x08
NbSmuServiceRequest Exit
NbFmInitLclkDpmRcActivity F14 Exit [0x0]
NbLclkDpmFeature Exit [0x0]
AmdInitMid: End
agesawrapper_amdinitmid() returned AGESA_SUCCESS
ader - leaving domain_enable_resources.
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 subsystem <- 1022/1510
PCI: 00:01.0 cmd <- 07
PCI: 00:01.1 subsystem <- 1022/1510
PCI: 00:01.1 cmd <- 02
PCI: 00:11.0 subsystem <- 1022/1510
PCI: 00:11.0 cmd <- 03
PCI: 00:12.0 subsystem <- 1022/1510
PCI: 00:12.0 cmd <- 02
PCI: 00:12.2 subsystem <- 1022/1510
PCI: 00:12.2 cmd <- 02
PCI: 00:13.0 subsystem <- 1022/1510
PCI: 00:13.0 cmd <- 02
PCI: 00:13.2 subsystem <- 1022/1510
PCI: 00:13.2 cmd <- 02
PCI: 00:14.0 subsystem <- 1022/1510
PCI: 00:14.0 cmd <- 403
PCI: 00:14.2 subsystem <- 1022/1510
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 1022/1510
PCI: 00:14.3 cmd <- 0f
PCI: 00:14.4 bridge ctrl <- 0003
PCI: 00:14.4 cmd <- 21
PCI: 00:14.5 subsystem <- 1022/1510
PCI: 00:14.5 cmd <- 02
PCI: 00:15.0 bridge ctrl <- 0003
PCI: 00:15.0 cmd <- 00
PCI: 00:15.1 bridge ctrl <- 0003
PCI: 00:15.1 cmd <- 07
PCI: 00:15.2 bridge ctrl <- ffff
PCI: 00:15.2 cmd <- ffff
PCI: 00:18.0 subsystem <- 1022/1510
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 1022/1510
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1022/1510
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 subsystem <- 1022/1510
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 subsystem <- 1022/1510
PCI: 00:18.4 cmd <- 00
PCI: 00:18.5 subsystem <- 1022/1510
PCI: 00:18.5 cmd <- 00
PCI: 00:18.6 subsystem <- 1022/1510
PCI: 00:18.6 cmd <- 00
PCI: 00:18.7 subsystem <- 1022/1510
PCI: 00:18.7 cmd <- 00
PCI: 03:00.0 cmd <- 03
done.
BS: BS_DEV_ENABLE times (us): entry 5 run 11993 exit 0
Initializing devices...
Root Device init ...
Root Device init finished in 0 usecs
CPU_CLUSTER: 0 init ...
start_eip=0x00001000, code_size=0x00000031
Initializing CPU #0
CPU: vendor AMD device 500f20
CPU: family 14, model 02, stepping 00
Model 14 Init.
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Enabling cache
Setting up local APIC... apic_id: 0x00 done.
model_14_init done.
CPU #0 initialized
CPU1: stack_base 00138000, stack_end 00138ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
Waiting for 1 CPUS to stop
CPU: vendor AMD device 500f20
CPU: family 14, model 02, stepping 00
Model 14 Init.
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Enabling cache
Setting up local APIC... apic_id: 0x01 done.
model_14_init done.
CPU #1 initialized
All AP CPUs stopped (76 loops)
CPU0: stack: 00139000 - 0013a000, lowest used address 00139700, stack used: 2304 bytes
CPU1: stack: 00138000 - 00139000, lowest used address 00138e04, stack used: 508 bytes
CPU_CLUSTER: 0 init finished in 12688 usecs
DOMAIN: 0000 init ...
DOMAIN: 0000 init finished in 1 usecs
PCI: 00:00.0 init ...
Northbridge init
PCI: 00:00.0 init finished in 2 usecs
PCI: 00:01.0 init ...
PCI: 00:01.0 init finished in 1 usecs
PCI: 00:01.1 init ...
PCI: 00:01.1 init finished in 1 usecs
PCI: 00:11.0 init ...
PCI: 00:11.0 init finished in 1 usecs
PCI: 00:14.0 init ...
PCI: 00:14.0 init finished in 1 usecs
PCI: 00:14.3 init ...
SB800 - Late.c - lpc_init - Start.
RTC Init
RTC: coreboot checksum invalid
SB800 - Late.c - lpc_init - End.
PCI: 00:14.3 init finished in 416 usecs
PCI: 00:18.0 init ...
PCI: 00:18.0 init finished in 1 usecs
PCI: 00:18.1 init ...
PCI: 00:18.1 init finished in 1 usecs
PCI: 00:18.2 init ...
PCI: 00:18.2 init finished in 1 usecs
PCI: 00:18.3 init ...
PCI: 00:18.3 init finished in 1 usecs
PCI: 00:18.4 init ...
PCI: 00:18.4 init finished in 1 usecs
PCI: 00:18.5 init ...
PCI: 00:18.5 init finished in 1 usecs
PCI: 00:18.6 init ...
PCI: 00:18.6 init finished in 1 usecs
PCI: 00:18.7 init ...
PCI: 00:18.7 init finished in 1 usecs
PNP: 002e.2 init ...
PNP: 002e.2 init finished in 1 usecs
PNP: 002e.5 init ...
PNP: 002e.5 init finished in 24 usecs
PNP: 002e.307 init ...
PNP: 002e.307 init finished in 1 usecs
PNP: 002e.9 init ...
PNP: 002e.9 init finished in 1 usecs
PNP: 002e.a init ...
CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 50b40 size 5b0
set power off after power fail
PNP: 002e.a init finished in 437 usecs
PNP: 002e.b init ...
PNP: 002e.b init finished in 1 usecs
PNP: 002e.d init ...
PNP: 002e.d init finished in 1 usecs
PCI: 03:00.0 init ...
PCI: 03:00.0 init finished in 1 usecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:04.0: enabled 0
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.1: enabled 0
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 0
PNP: 002e.107: enabled 0
PNP: 002e.207: enabled 0
PNP: 002e.307: enabled 1
PNP: 002e.407: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 1
PNP: 002e.109: enabled 0
PNP: 002e.209: enabled 0
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 1
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PNP: 002e.d: enabled 1
PNP: 002e.e: enabled 0
PNP: 002e.f: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:15.1: enabled 1
PCI: 00:15.2: enabled 1
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
APIC: 01: enabled 1
PCI: 03:00.0: enabled 1
BS: BS_DEV_INIT times (us): entry 0 run 14675 exit 0
CBMEM:
IMD: root @ c7fff000 254 entries.
IMD: root @ c7ffec00 62 entries.
Moving GDT to c7ffea00...ok
Finalize devices...
Devices finalized
AmdInitLate: Start
CreatSystemTable: Start
SSDT is created
CreatSystemTable: End
DispatchCpuFeatures: LateStart
DispatchCpuFeatures: LateEnd
AmdCpuLate: Start
AmdCpuLate: End
PcieFmAlibBuildAcpiTable Enter
PcieFmAlibBuildAcpiTable Exit[0x0]
AmdInitLate: End
agesawrapper_amdinitlate() returned AGESA_SUCCESS
~Fn2_040 = 1
~Fn2_044 = 109
~Fn2_048 = 201
~Fn2_04c = 309
~Fn2_098 = 8d0f0f1f
~Fn2_09C_d0f0f1f = 2002
~Fn2_098 = 8d0f2f1f
~Fn2_09C_d0f2f1f = 2000
~Fn2_098 = 8d0f4009
~Fn2_09C_d0f4009 = 2010
~Fn2_098 = 8d0f8f1f
~Fn2_09C_d0f8f1f = 2000
~Fn2_098 = 8d0fc01f
~Fn2_09C_d0fc01f = 2000
~Fn2_098 = 8d0f0f1e
~Fn2_09C_d0f0f1e = 5220
~Fn2_098 = 8d0f2f1e
~Fn2_09C_d0f2f1e = 5020
~Fn2_098 = 8d0f8f1e
~Fn2_09C_d0f8f1e = 5020
~Fn2_098 = 8d0fcf1e
~Fn2_09C_d0fcf1e = 5020
~Fn2_098 = 8d0f0f38
~Fn2_09C_d0f0f38 = 0
~Fn2_094 = 3e40888a
~Fn2_098 = 8d0fe006
~Fn2_09C_d0fe006 = f
~Fn2_098 = 8d0f0f31
~Fn2_09C_d0f0f31 = 6ffa
~Fn2_098 = 8d0f2f31
~Fn2_09C_d0f2f31 = 1a
~Fn2_098 = 8d0f8f31
~Fn2_09C_d0f8f31 = 1a
~Fn2_098 = 8d0fc031
~Fn2_09C_d0fc031 = 1a
~Fn2_098 = 8d0f0f00
~Fn2_09C_d0f0f00 = 32
~Fn2_098 = 8d0f0f08
~Fn2_09C_d0f0f08 = 32
~Fn2_098 = 8d0f0f06
~Fn2_09C_d0f0f06 = ff6
~Fn2_098 = 8d0f0f0a
~Fn2_09C_d0f0f0a = ff6
~Fn2_098 = 8d0f0f02
~Fn2_09C_d0f0f02 = ff6
~Fn2_098 = 8d0f8006
~Fn2_09C_d0f8006 = 6db
~Fn2_098 = 8d0f800a
~Fn2_09C_d0f800a = 6db
~Fn2_098 = 8d0f8106
~Fn2_09C_d0f8106 = 6db
~Fn2_098 = 8d0f810a
~Fn2_09C_d0f810a = 6db
~Fn2_098 = 8d0fc006
~Fn2_09C_d0fc006 = 6db
~Fn2_098 = 8d0fc00a
~Fn2_09C_d0fc00a = 6db
~Fn2_098 = 8d0fc00e
~Fn2_09C_d0fc00e = 6db
~Fn2_098 = 8d0fc012
~Fn2_09C_d0fc012 = 6db
~Fn2_098 = 8d0f8002
~Fn2_09C_d0f8002 = 6db
~Fn2_098 = 8d0f8102
~Fn2_09C_d0f8102 = 6db
~Fn2_098 = 8d0fc002
~Fn2_09C_d0fc002 = 6db
~Fn2_098 = 8d0f2002
~Fn2_09C_d0f2002 = ff6
~Fn2_098 = 8d0f2102
~Fn2_09C_d0f2102 = ff6
~Fn2_098 = 8d0fe003
~Fn2_09C_d0fe003 = 4820
~Fn2_098 = 8d0f2030
~Fn2_09C_d0f2030 = 4
~Fn2_098 = 8d0f2130
~Fn2_09C_d0f2130 = 4
~Fn2_098 = 8d0f0f13
~Fn2_09C_d0f0f13 = 40a3
~Fn2_098 = 8d0f812f
~Fn2_09C_d0f812f = a1
~Fn2_098 = 8d0fc000
~Fn2_09C_d0fc000 = 3
~Fn2_098 = 8d0f0f10
~Fn2_09C_d0f0f10 = 1337
~Fn2_090 = 6600000
agesawrapper_amdS3Save() returned AGESA_SUCCESS
Manufacturer: ef
SF: Detected W25Q32 with sector size 0x1000, total 0x400000
SF: Successfully erased 4096 bytes @ 0xffff1000
Manufacturer: ef
SF: Detected W25Q32 with sector size 0x1000, total 0x400000
SF: Successfully erased 4096 bytes @ 0xffff0000
BS: BS_POST_DEVICE times (us): entry 66 run 4 exit 175672
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0
Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
Writing IRQ routing tables to 0xc7e6b000...write_pirq_routing_table done.
PIRQ table: 48 bytes.
Wrote the mp table end at: 000f0410 - 000f05fc
Wrote the mp table end at: c7e6a010 - c7e6a1fc
MP table: 508 bytes.
CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
CBFS: Locating 'fallback/dsdt.aml'
CBFS: Found @ offset 59400 size 24c9
CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
CBFS: Locating 'fallback/slic'
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at c7e46000.
ACPI: * FACS
ACPI: * DSDT
ACPI: * FADT
ACPI_BLK_BASE: 0x0800
ACPI: added table 1/32, length now 40
ACPI: * SSDT
ACPI: added table 2/32, length now 44
ACPI: * MCFG
ACPI: * TCPA
TCPA log created at c7e36000
ACPI: added table 3/32, length now 48
ACPI: * MADT
ACPI: added table 4/32, length now 52
current = c7e48980
ACPI: added table 5/32, length now 56
ACPI: * SRAT at c7e489a8
AGESA SRAT table NULL. Skipping.
ACPI: * SLIT at c7e489a8
AGESA SLIT table NULL. Skipping.
ACPI: * AGESA ALIB SSDT at c7e489b0
ACPI: added table 6/32, length now 60
ACPI: * AGESA SSDT Pstate at c7e4a040
ACPI: added table 7/32, length now 64
CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
CBFS: Locating 'pci1002,9802.rom'
CBFS: 'pci1002,9802.rom' not found.
ACPI: * HPET
ACPI: added table 8/32, length now 68
ACPI: done.
ACPI tables: 17504 bytes.
smbios_write_tables: c7e35000
Root Device (ASROCK E350M1)
CPU_CLUSTER: 0 (AMD Family 14h Root Complex)
APIC: 00 (AMD CPU Family 14h Model 00h-0Fh)
DOMAIN: 0000 (AMD Family 14h Root Complex)
PCI: 00:00.0 (AMD Family 14h Northbridge)
PCI: 00:01.0 (AMD Family 14h Northbridge)
PCI: 00:01.1 (AMD Family 14h Northbridge)
PCI: 00:04.0 (AMD Family 14h Northbridge)
PCI: 00:05.0 (AMD Family 14h Northbridge)
PCI: 00:06.0 (AMD Family 14h Northbridge)
PCI: 00:07.0 (AMD Family 14h Northbridge)
PCI: 00:08.0 (AMD Family 14h Northbridge)
PCI: 00:11.0 (ATI SB800)
PCI: 00:12.0 (ATI SB800)
PCI: 00:12.2 (ATI SB800)
PCI: 00:13.0 (ATI SB800)
PCI: 00:13.2 (ATI SB800)
PCI: 00:14.0 (ATI SB800)
I2C: 00:50 (unknown)
I2C: 00:51 (unknown)
PCI: 00:14.1 (ATI SB800)
PCI: 00:14.2 (ATI SB800)
PCI: 00:14.3 (ATI SB800)
PNP: 002e.0 (NUVOTON NCT5572D Super I/O)
PNP: 002e.1 (NUVOTON NCT5572D Super I/O)
PNP: 002e.2 (NUVOTON NCT5572D Super I/O)
PNP: 002e.3 (NUVOTON NCT5572D Super I/O)
PNP: 002e.5 (NUVOTON NCT5572D Super I/O)
PNP: 002e.6 (NUVOTON NCT5572D Super I/O)
PNP: 002e.107 (NUVOTON NCT5572D Super I/O)
PNP: 002e.207 (NUVOTON NCT5572D Super I/O)
PNP: 002e.307 (NUVOTON NCT5572D Super I/O)
PNP: 002e.407 (NUVOTON NCT5572D Super I/O)
PNP: 002e.8 (NUVOTON NCT5572D Super I/O)
PNP: 002e.9 (NUVOTON NCT5572D Super I/O)
PNP: 002e.109 (NUVOTON NCT5572D Super I/O)
PNP: 002e.209 (NUVOTON NCT5572D Super I/O)
PNP: 002e.309 (NUVOTON NCT5572D Super I/O)
PNP: 002e.a (NUVOTON NCT5572D Super I/O)
PNP: 002e.b (NUVOTON NCT5572D Super I/O)
PNP: 002e.c (NUVOTON NCT5572D Super I/O)
PNP: 002e.d (NUVOTON NCT5572D Super I/O)
PNP: 002e.e (NUVOTON NCT5572D Super I/O)
PNP: 002e.f (NUVOTON NCT5572D Super I/O)
PCI: 00:14.4 (ATI SB800)
PCI: 00:14.5 (ATI SB800)
PCI: 00:15.0 (ATI SB800)
PCI: 00:15.1 (ATI SB800)
PCI: 00:15.2 (ATI SB800)
PCI: 00:15.3 (ATI SB800)
PCI: 00:16.0 (ATI SB800)
PCI: 00:16.2 (ATI SB800)
PCI: 00:18.0 (AMD Family 14h Northbridge)
PCI: 00:18.1 (AMD Family 14h Northbridge)
PCI: 00:18.2 (AMD Family 14h Northbridge)
PCI: 00:18.3 (AMD Family 14h Northbridge)
PCI: 00:18.4 (AMD Family 14h Northbridge)
PCI: 00:18.5 (AMD Family 14h Northbridge)
PCI: 00:18.6 (AMD Family 14h Northbridge)
PCI: 00:18.7 (AMD Family 14h Northbridge)
APIC: 01 (unknown)
PCI: 03:00.0 (unknown)
SMBIOS tables: 339 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 77f7
Writing coreboot table at 0xc7e6c000
CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 50b40 size 5b0
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-00000000c7e34fff: RAM
3. 00000000c7e35000-00000000c7ffffff: CONFIGURATION TABLES
4. 00000000c8000000-00000000dfffffff: RESERVED
5. 00000000f8000000-00000000fbffffff: RESERVED
6. 0000000100000000-000000021effffff: RAM
CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
FMAP: Found "FLASH" version 1.1 at 0.
FMAP: base = ffc00000 size = 400000 #areas = 3
Wrote coreboot table at: c7e6c000, 0x874 bytes, checksum a95
coreboot table: 2188 bytes.
IMD ROOT 0. c7fff000 00001000
IMD SMALL 1. c7ffe000 00001000
CONSOLE 2. c7fde000 00020000
TIME STAMP 3. c7fdd000 00000400
ROMSTG STCK 4. c7fc5000 00018000
ACPISCRATCH 5. c7f95000 00030000
ACPI RESUME 6. c7e74000 00121000
COREBOOT 7. c7e6c000 00008000
IRQ TABLE 8. c7e6b000 00001000
SMP TABLE 9. c7e6a000 00001000
ACPI 10. c7e46000 00024000
TCPA LOG 11. c7e36000 00010000
SMBIOS 12. c7e35000 00000800
IMD small region:
IMD ROOT 0. c7ffec00 00000400
GDT 1. c7ffea00 00000200
BS: BS_WRITE_TABLES times (us): entry 0 run 5080 exit 0
CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 94500 size c1ed
Loading segment from ROM address 0xffc94638
code (compression=1)
New segment dstaddr 0xe92e0 memsize 0x16d20 srcaddr 0xffc94670 filesize 0xc1b5
Loading segment from ROM address 0xffc94654
Entry Point 0x000ff06e
Bounce Buffer at c7bf6000, 2353248 bytes
Loading Segment: addr: 0x00000000000e92e0 memsz: 0x0000000000016d20 filesz: 0x000000000000c1b5
lb: [0x0000000000100000, 0x000000000021f430)
Post relocation: addr: 0x00000000000e92e0 memsz: 0x0000000000016d20 filesz: 0x000000000000c1b5
using LZMA
[ 0x000e92e0, 00100000, 0x00100000) <- ffc94670
dest 000e92e0, end 00100000, bouncebuffer c7bf6000
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 23997 exit 0
Jumping to boot code at 000ff06e(c7e6c000)
CPU0: stack: 00139000 - 0013a000, lowest used address 00139700, stack used: 2304 bytes
entry = 0x000ff06e
lb_start = 0x00100000
lb_size = 0x0011f430
buffer = 0xc7bf6000
SeaBIOS (version rel-1.10.0-25-g1415d46)
BUILD: gcc: (Debian 6.3.0-8) 6.3.0 20170221 binutils: (GNU Binutils for Debian) 2.27.90.20170221
Found coreboot cbmem console @ c7fde000
Found mainboard ASROCK E350M1
malloc preinit
Relocating init from 0x000ea5c0 to 0xc7deb900 (size 38496)
malloc init
Found CBFS header at 0xffc00138
Add romfile: cbfs master header (size=32)
Add romfile: fallback/romstage (size=224020)
Add romfile: fallback/ramstage (size=104846)
Add romfile: config (size=626)
Add romfile: revision (size=576)
Add romfile: cmos_layout.bin (size=1456)
Add romfile: pci1002,9802.rom (size=57856)
Add romfile: fallback/dsdt.aml (size=9417)
Add romfile: img/coreinfo (size=108756)
Add romfile: img/nvramcui (size=123516)
Add romfile: fallback/payload (size=49645)
Add romfile: img/tint (size=68324)
Add romfile: img/memtest (size=180268)
Add romfile: bootsplash.jpg (size=170591)
Add romfile: etc/threads (size=8)
Add romfile: (size=3051672)
Add romfile: s3nv (size=32768)
Add romfile: (size=31064)
Add romfile: bootblock (size=1584)
init ivt
init bda
init bios32
init PMM
init keyboard
init mouse
init pic
Copying data 8@0xffd06ee8 to 8@0x00006dbc
math cp init
PCI probe
PCI device 00:00.0 (vd=1022:1510 c=0600)
PCI device 00:01.0 (vd=1002:9802 c=0300)
PCI device 00:01.1 (vd=1002:1314 c=0403)
PCI device 00:11.0 (vd=1002:4391 c=0106)
PCI device 00:12.0 (vd=1002:4397 c=0c03)
PCI device 00:12.2 (vd=1002:4396 c=0c03)
PCI device 00:13.0 (vd=1002:4397 c=0c03)
PCI device 00:13.2 (vd=1002:4396 c=0c03)
PCI device 00:14.0 (vd=1002:4385 c=0c05)
PCI device 00:14.2 (vd=1002:4383 c=0403)
PCI device 00:14.3 (vd=1002:439d c=0601)
PCI device 00:14.4 (vd=1002:4384 c=0604)
PCI device 00:14.5 (vd=1002:4399 c=0c03)
PCI device 00:15.0 (vd=1002:43a0 c=0604)
PCI device 00:15.1 (vd=1002:43a1 c=0604)
PCI device 00:18.0 (vd=1022:1700 c=0600)
PCI device 00:18.1 (vd=1022:1701 c=0600)
PCI device 00:18.2 (vd=1022:1702 c=0600)
PCI device 00:18.3 (vd=1022:1703 c=0600)
PCI device 00:18.4 (vd=1022:1704 c=0600)
PCI device 00:18.5 (vd=1022:1718 c=0600)
PCI device 00:18.6 (vd=1022:1716 c=0600)
PCI device 00:18.7 (vd=1022:1719 c=0600)
PCI device 03:00.0 (vd=10ec:8168 c=0200)
Found 24 PCI devices (max PCI bus is 03)
Relocating coreboot bios tables
Copying SMBIOS entry point from 0xc7e35000 to 0x000f3c00
Copying ACPI RSDP from 0xc7e46000 to 0x000f3bd0
Copying MPTABLE from 0xc7e6a000/c7e6a010 to 0x000f39d0
Copying PIR from 0xc7e6b000 to 0x000f39a0
rsdp=0x000f3bd0
rsdt=0xc7e46030
table(50434146)=0xc7e48750
pm_tmr_blk=808
Using pmtimer, ioport 0x808
init timer
init usb
EHCI init on dev 00:12.2 (regs=0xf014c020)
/c7de9000\ Start thread
EHCI init on dev 00:13.2 (regs=0xf014d020)
/c7de7000\ Start thread
OHCI init on dev 00:12.0 (regs=0xf0148000)
/c7de6000\ Start thread
OHCI init on dev 00:13.0 (regs=0xf0149000)
/c7de5000\ Start thread
OHCI init on dev 00:14.5 (regs=0xf014a000)
/c7de4000\ Start thread
init ps2port
/c7de3000\ Start thread
init ahci
AHCI controller at 00:11.0, iobase 0xf014b000, irq 0
AHCI: cap 0xf332ff05, ports_impl 0x3f
/c7de2000\ Start thread
|c7de2000| AHCI/0: probing
|c7de2000| AHCI/0: link up
/c7de0000\ Start thread
|c7de0000| AHCI/1: probing
/c7ddf000\ Start thread
|c7ddf000| AHCI/2: probing
/c7ddd000\ Start thread
|c7ddd000| AHCI/3: probing
/c7ddc000\ Start thread
|c7ddc000| AHCI/4: probing
/c7dda000\ Start thread
|c7dda000| AHCI/5: probing
Registering bootable: Payload [memtest] (type:32 prio:9999 data:ffcb1380)
Registering bootable: Payload [tint] (type:32 prio:9999 data:ffca0840)
Registering bootable: Payload [nvramcui] (type:32 prio:9999 data:ffc76340)
Registering bootable: Payload [coreinfo] (type:32 prio:9999 data:ffc5ba40)
Scan for VGA option rom
Attempting to init PCI bdf 00:01.0 (vd 1002:9802)
|c7ddd000| AHCI/3: link down
|c7ddf000| AHCI/2: link down
|c7de0000| AHCI/1: link down
|c7dda000| AHCI/5: link down
|c7ddc000| AHCI/4: link down
\c7ddd000/ End thread
\c7ddf000/ End thread
\c7de0000/ End thread
\c7dda000/ End thread
\c7ddc000/ End thread
Uncompressing data 33379@0xc7dd1d90 to 57856@0x000c0000
/c7de0000\ Start thread
/c7ddf000\ Start thread
Running option rom at c000:0003
/c7dde000\ Start thread
/c7ddd000\ Start thread
\c7ddd000/ End thread
/c7ddd000\ Start thread
/c7ddc000\ Start thread
/c7dda000\ Start thread
/c7dd9000\ Start thread
/c7dd8000\ Start thread
/c7dd7000\ Start thread
/c7dd6000\ Start thread
/c7dd5000\ Start thread
/c7dd4000\ Start thread
/c7dd3000\ Start thread
/c7dd2000\ Start thread
/c7dd1000\ Start thread
/c7dd0000\ Start thread
/c7dcf000\ Start thread
/c7dce000\ Start thread
/c7dcd000\ Start thread
/c7dcc000\ Start thread
/c7dcb000\ Start thread
Turning on vga text mode console
|c7dd1000| set_address 0xc7de8e70
\c7dd8000/ End thread
\c7dda000/ End thread
\c7ddd000/ End thread
\c7dde000/ End thread
\c7de0000/ End thread
\c7dd7000/ End thread
\c7dd9000/ End thread
\c7ddc000/ End thread
\c7ddf000/ End thread
SeaBIOS (version rel-1.10.0-25-g1415d46)
Scan for option roms
Attempting to init PCI bdf 00:00.0 (vd 1022:1510)
Attempting to init PCI bdf 00:01.1 (vd 1002:1314)
Attempting to init PCI bdf 00:14.0 (vd 1002:4385)
Attempting to init PCI bdf 00:14.2 (vd 1002:4383)
Attempting to init PCI bdf 00:14.3 (vd 1002:439d)
Attempting to init PCI bdf 00:14.4 (vd 1002:4384)
Attempting to init PCI bdf 00:15.0 (vd 1002:43a0)
Attempting to init PCI bdf 00:15.1 (vd 1002:43a1)
Attempting to init PCI bdf 00:18.0 (vd 1022:1700)
Attempting to init PCI bdf 00:18.1 (vd 1022:1701)
Attempting to init PCI bdf 00:18.2 (vd 1022:1702)
Attempting to init PCI bdf 00:18.3 (vd 1022:1703)
Attempting to init PCI bdf 00:18.4 (vd 1022:1704)
Attempting to init PCI bdf 00:18.5 (vd 1022:1718)
Attempting to init PCI bdf 00:18.6 (vd 1022:1716)
Attempting to init PCI bdf 00:18.7 (vd 1022:1719)
Attempting to init PCI bdf 03:00.0 (vd 10ec:8168)
Press ESC for boot menu.
Checking for bootsplash
Copying romfile 'bootsplash.jpg' (len 170591)
Copying data 170591@0xffcdd438 to 170591@0xc7da15a0
\c7de7000/ End thread
\c7de9000/ End thread
|c7dd1000| config_usb: 0xc7dea0a0
|c7dd1000| device rev=0100 cls=00 sub=00 proto=00 size=8
|c7dd1000| usb_hid_setup 0xc7dea0a0
|c7dd1000| USB mouse initialized
\c7dd1000/ End thread
\c7dd3000/ End thread
\c7dd6000/ End thread
\c7dcc000/ End thread
\c7dce000/ End thread
\c7dd0000/ End thread
\c7dd2000/ End thread
\c7dd5000/ End thread
\c7dcb000/ End thread
\c7dcd000/ End thread
\c7dcf000/ End thread
\c7dd4000/ End thread
\c7de4000/ End thread
\c7de5000/ End thread
\c7de6000/ End thread
start showing bootsplash
VESA 3.0
VENDOR: (C) 1988-2010, AMD Technologies Inc.
PRODUCT: WRESTLER
Decoding bootsplash.jpg
Finding vesa mode with dimensions 1024/768
mode: 0117
framebuffer: 0xe0000000
bytes per scanline: 2048
bits per pixel: 16
Decompressing bootsplash.jpg
Switching to graphics mode
Showing bootsplash picture
|c7de3000| PS2 keyboard initialized
\c7de3000/ End thread
Bootsplash copy complete
Turning on vga text mode console
SeaBIOS (version rel-1.10.0-25-g1415d46)
|c7de2000| AHCI/0: ... finished, status 0x51, ERROR 0x4
|c7de2000| AHCI/0: supported modes: udma 5, multi-dma 2, pio 4
|c7de2000| AHCI/0: Set transfer mode to UDMA-5
|c7de2000| AHCI/0: registering: "AHCI/0: WDC WD20EARS-60MVWB0 ATA-8 Hard-Disk (1863 GiBytes)"
|c7de2000| Registering bootable: AHCI/0: WDC WD20EARS-60MVWB0 ATA-8 Hard-Disk (1863 GiBytes) (type:2 prio:103 data:f3930)
\c7de2000/ End thread
All threads complete.
Searching bootorder for: HALT
Mapping hd drive 0x000f3930 to 0
drive 0x000f3930: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=3907029168
finalize PMM
malloc finalize
Space available for UMB: ce800-ee800, f0000-f3930
Returned 253952 bytes of ZoneHigh
e820 map has 7 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 00000000c7e33000 = 1 RAM
4: 00000000c7e33000 - 00000000e0000000 = 2 RESERVED
5: 00000000f8000000 - 00000000fc000000 = 2 RESERVED
6: 0000000100000000 - 000000021f000000 = 1 RAM
Jump to int19
enter handle_19:
NULL
Booting from Hard Disk...
Booting from 0000:7c00