| *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| ing up static northbridge registers... done |
| [DEBUG] Initializing Graphics... |
| [DEBUG] Back from systemagent_early_init() |
| [DEBUG] SB: Resume from S3 detected. |
| [INFO ] Intel ME early init |
| [INFO ] Intel ME firmware is ready |
| [DEBUG] ME: Requested 0MB UMA |
| [DEBUG] Starting native Platform init |
| [DEBUG] DMI: Running at X4 @ 5000MT/s |
| [DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes) |
| [DEBUG] Trying stored timings. |
| [DEBUG] Starting Ivy Bridge RAM training (fast boot). |
| [DEBUG] 100MHz reference clock support: yes |
| [DEBUG] PLL_REF100_CFG value: 0x7 |
| [DEBUG] Trying CAS 11, tCK 320. |
| [DEBUG] Trying CAS 10, tCK 365. |
| [DEBUG] Trying CAS 9, tCK 384. |
| [DEBUG] Found compatible clock, CAS pair. |
| [DEBUG] Selected DRAM frequency: 666 MHz |
| [DEBUG] Selected CAS latency : 9T |
| [DEBUG] MPLL busy... done in 60 us |
| [DEBUG] MPLL frequency is set at : 666 MHz |
| [DEBUG] Done dimm mapping |
| [DEBUG] Update PCI-E configuration space: |
| [DEBUG] PCI(0, 0, 0)[a0] = 0 |
| [DEBUG] PCI(0, 0, 0)[a4] = 4 |
| [DEBUG] PCI(0, 0, 0)[bc] = 82a00000 |
| [DEBUG] PCI(0, 0, 0)[a8] = 7d600000 |
| [DEBUG] PCI(0, 0, 0)[ac] = 4 |
| [DEBUG] PCI(0, 0, 0)[b8] = 80000000 |
| [DEBUG] PCI(0, 0, 0)[b0] = 80a00000 |
| [DEBUG] PCI(0, 0, 0)[b4] = 80800000 |
| [DEBUG] Done memory map |
| [DEBUG] Done io registers |
| [DEBUG] t123: 1912, 6000, 7620 |
| [NOTE ] ME: Wrong mode : 2 |
| [NOTE ] ME: FWS2: 0x100a0140 |
| [NOTE ] ME: Bist in progress: 0x0 |
| [NOTE ] ME: ICC Status : 0x0 |
| [NOTE ] ME: Invoke MEBx : 0x0 |
| [NOTE ] ME: CPU replaced : 0x0 |
| [NOTE ] ME: MBP ready : 0x0 |
| [NOTE ] ME: MFS failure : 0x1 |
| [NOTE ] ME: Warm reset req : 0x0 |
| [NOTE ] ME: CPU repl valid : 0x1 |
| [NOTE ] ME: (Reserved) : 0x0 |
| [NOTE ] ME: FW update req : 0x0 |
| [NOTE ] ME: (Reserved) : 0x0 |
| [NOTE ] ME: Current state : 0xa |
| [NOTE ] ME: Current PM event: 0x0 |
| [NOTE ] ME: Progress code : 0x1 |
| [NOTE ] PASSED! Tell ME that DRAM is ready |
| [NOTE ] ME: ME is reporting as disabled, so not waiting for a response. |
| [NOTE ] ME: FWS2: 0x100a0140 |
| [NOTE ] ME: Bist in progress: 0x0 |
| [NOTE ] ME: ICC Status : 0x0 |
| [NOTE ] ME: Invoke MEBx : 0x0 |
| [NOTE ] ME: CPU replaced : 0x0 |
| [NOTE ] ME: MBP ready : 0x0 |
| [NOTE ] ME: MFS failure : 0x1 |
| [NOTE ] ME: Warm reset req : 0x0 |
| [NOTE ] ME: CPU repl valid : 0x1 |
| [NOTE ] ME: (Reserved) : 0x0 |
| [NOTE ] ME: FW update req : 0x0 |
| [NOTE ] ME: (Reserved) : 0x0 |
| [NOTE ] ME: Current state : 0xa |
| [NOTE ] ME: Current PM event: 0x0 |
| [NOTE ] ME: Progress code : 0x1 |
| [NOTE ] ME: Requested BIOS Action: No DID Ack received |
| [DEBUG] ME: FW Partition Table : OK |
| [DEBUG] ME: Bringup Loader Failure : NO |
| [DEBUG] ME: Firmware Init Complete : NO |
| [DEBUG] ME: Manufacturing Mode : YES |
| [DEBUG] ME: Boot Options Present : NO |
| [DEBUG] ME: Update In Progress : NO |
| [DEBUG] ME: Current Working State : Initializing |
| [DEBUG] ME: Current Operation State : Bring up |
| [DEBUG] ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| [DEBUG] ME: Error Code : No Error |
| [DEBUG] ME: Progress Phase : BUP Phase |
| [DEBUG] ME: Power Management Event : Clean Moff->Mx wake |
| [DEBUG] ME: Progress Phase State : Check to see if straps say ME DISABLED |
| [DEBUG] memcfg DDR3 ref clock 133 MHz |
| [DEBUG] memcfg DDR3 clock 1330 MHz |
| [DEBUG] memcfg channel assignment: A: 0, B 1, C 2 |
| [DEBUG] memcfg channel[0] config (00620020): |
| [DEBUG] ECC inactive |
| [DEBUG] enhanced interleave mode on |
| [DEBUG] rank interleave on |
| [DEBUG] DIMMA 8192 MB width x8 dual rank, selected |
| [DEBUG] DIMMB 0 MB width x8 single rank |
| [DEBUG] memcfg channel[1] config (00620020): |
| [DEBUG] ECC inactive |
| [DEBUG] enhanced interleave mode on |
| [DEBUG] rank interleave on |
| [DEBUG] DIMMA 8192 MB width x8 dual rank, selected |
| [DEBUG] DIMMB 0 MB width x8 single rank |
| [DEBUG] SMM Memory Map |
| [DEBUG] SMRAM : 0x80000000 0x800000 |
| [DEBUG] Subregion 0: 0x80000000 0x300000 |
| [DEBUG] Subregion 1: 0x80300000 0x100000 |
| [DEBUG] Subregion 2: 0x80400000 0x400000 |
| [DEBUG] S3 Resume |
| [DEBUG] BS: romstage times (exec / console): total (unknown) / 1 ms |
| |
| |
| [NOTE ] coreboot-4.19-293-gdb4b71ff10 Mon Feb 06 19:30:57 UTC 2023 x86_32 postcar starting (log level: 8)... |
| [DEBUG] S3 Resume |
| [DEBUG] Jumping to image. |
| |
| |
| [NOTE ] coreboot-4.19-293-gdb4b71ff10 Mon Feb 06 19:30:57 UTC 2023 x86_32 ramstage starting (log level: 8)... |
| [DEBUG] S3 Resume |
| [INFO ] Enumerating buses... |
| [SPEW ] Show all devs... Before device enumeration. |
| [SPEW ] Root Device: enabled 1 |
| [SPEW ] CPU_CLUSTER: 0: enabled 1 |
| [SPEW ] DOMAIN: 0000: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PCI: 00:01.0: enabled 0 |
| [SPEW ] PCI: 00:01.1: enabled 0 |
| [SPEW ] PCI: 00:01.2: enabled 0 |
| [SPEW ] PCI: 00:02.0: enabled 1 |
| [SPEW ] PCI: 00:04.0: enabled 0 |
| [SPEW ] PCI: 00:06.0: enabled 0 |
| [SPEW ] PCI: 00:14.0: enabled 1 |
| [SPEW ] PCI: 00:16.0: enabled 1 |
| [SPEW ] PCI: 00:16.1: enabled 0 |
| [SPEW ] PCI: 00:16.2: enabled 0 |
| [SPEW ] PCI: 00:16.3: enabled 0 |
| [SPEW ] PCI: 00:19.0: enabled 1 |
| [SPEW ] PCI: 00:1a.0: enabled 1 |
| [SPEW ] PCI: 00:1b.0: enabled 1 |
| [SPEW ] PCI: 00:1c.0: enabled 1 |
| [SPEW ] PCI: 00:1c.1: enabled 1 |
| [SPEW ] PCI: 00:1c.2: enabled 1 |
| [SPEW ] PCI: 00:1c.3: enabled 0 |
| [SPEW ] PCI: 00:1c.4: enabled 0 |
| [SPEW ] PCI: 00:1c.5: enabled 0 |
| [SPEW ] PCI: 00:1c.6: enabled 0 |
| [SPEW ] PCI: 00:1c.7: enabled 0 |
| [SPEW ] PCI: 00:1d.0: enabled 1 |
| [SPEW ] PCI: 00:1e.0: enabled 0 |
| [SPEW ] PCI: 00:1f.0: enabled 1 |
| [SPEW ] PCI: 00:1f.2: enabled 1 |
| [SPEW ] PCI: 00:1f.3: enabled 1 |
| [SPEW ] PCI: 00:1f.5: enabled 0 |
| [SPEW ] PCI: 00:1f.6: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PNP: 00ff.1: enabled 1 |
| [SPEW ] PNP: 0c31.0: enabled 1 |
| [SPEW ] PNP: 00ff.2: enabled 1 |
| [SPEW ] I2C: 00:54: enabled 1 |
| [SPEW ] I2C: 00:55: enabled 1 |
| [SPEW ] I2C: 00:56: enabled 1 |
| [SPEW ] I2C: 00:57: enabled 1 |
| [SPEW ] I2C: 00:5c: enabled 1 |
| [SPEW ] I2C: 00:5d: enabled 1 |
| [SPEW ] I2C: 00:5e: enabled 1 |
| [SPEW ] I2C: 00:5f: enabled 1 |
| [SPEW ] Compare with tree... |
| [SPEW ] Root Device: enabled 1 |
| [SPEW ] CPU_CLUSTER: 0: enabled 1 |
| [SPEW ] DOMAIN: 0000: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PCI: 00:01.0: enabled 0 |
| [SPEW ] PCI: 00:01.1: enabled 0 |
| [SPEW ] PCI: 00:01.2: enabled 0 |
| [SPEW ] PCI: 00:02.0: enabled 1 |
| [SPEW ] PCI: 00:04.0: enabled 0 |
| [SPEW ] PCI: 00:06.0: enabled 0 |
| [SPEW ] PCI: 00:14.0: enabled 1 |
| [SPEW ] PCI: 00:16.0: enabled 1 |
| [SPEW ] PCI: 00:16.1: enabled 0 |
| [SPEW ] PCI: 00:16.2: enabled 0 |
| [SPEW ] PCI: 00:16.3: enabled 0 |
| [SPEW ] PCI: 00:19.0: enabled 1 |
| [SPEW ] PCI: 00:1a.0: enabled 1 |
| [SPEW ] PCI: 00:1b.0: enabled 1 |
| [SPEW ] PCI: 00:1c.0: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PCI: 00:1c.1: enabled 1 |
| [SPEW ] PCI: 00:1c.2: enabled 1 |
| [SPEW ] PCI: 00:1c.3: enabled 0 |
| [SPEW ] PCI: 00:1c.4: enabled 0 |
| [SPEW ] PCI: 00:1c.5: enabled 0 |
| [SPEW ] PCI: 00:1c.6: enabled 0 |
| [SPEW ] PCI: 00:1c.7: enabled 0 |
| [SPEW ] PCI: 00:1d.0: enabled 1 |
| [SPEW ] PCI: 00:1e.0: enabled 0 |
| [SPEW ] PCI: 00:1f.0: enabled 1 |
| [SPEW ] PNP: 00ff.1: enabled 1 |
| [SPEW ] PNP: 0c31.0: enabled 1 |
| [SPEW ] PNP: 00ff.2: enabled 1 |
| [SPEW ] PCI: 00:1f.2: enabled 1 |
| [SPEW ] PCI: 00:1f.3: enabled 1 |
| [SPEW ] I2C: 00:54: enabled 1 |
| [SPEW ] I2C: 00:55: enabled 1 |
| [SPEW ] I2C: 00:56: enabled 1 |
| [SPEW ] I2C: 00:57: enabled 1 |
| [SPEW ] I2C: 00:5c: enabled 1 |
| [SPEW ] I2C: 00:5d: enabled 1 |
| [SPEW ] I2C: 00:5e: enabled 1 |
| [SPEW ] I2C: 00:5f: enabled 1 |
| [SPEW ] PCI: 00:1f.5: enabled 0 |
| [SPEW ] PCI: 00:1f.6: enabled 1 |
| [DEBUG] Root Device scanning... |
| [SPEW ] scan_static_bus for Root Device |
| [DEBUG] CPU_CLUSTER: 0 enabled |
| [DEBUG] DOMAIN: 0000 enabled |
| [DEBUG] DOMAIN: 0000 scanning... |
| [DEBUG] PCI: pci_scan_bus for bus 00 |
| [SPEW ] PCI: 00:00.0 [8086/0000] ops |
| [DEBUG] PCI: 00:00.0 [8086/0154] enabled |
| [SPEW ] PCI: 00:01.0 [8086/0000] bus ops |
| [DEBUG] PCI: 00:01.0 [8086/0151] disabled |
| [SPEW ] PCI: 00:02.0 [8086/0000] ops |
| [DEBUG] PCI: 00:02.0 [8086/0166] enabled |
| [DEBUG] PCI: 00:04.0 [8086/0153] disabled |
| [SPEW ] PCI: 00:14.0 [8086/0000] ops |
| [DEBUG] PCI: 00:14.0 [8086/1e31] enabled |
| [SPEW ] PCI: 00:16.0 [8086/1e3a] ops |
| [DEBUG] PCI: 00:16.0 [8086/1e3a] enabled |
| [DEBUG] PCI: 00:16.1: Disabling device |
| [DEBUG] PCI: 00:16.2: Disabling device |
| [DEBUG] PCI: 00:16.3: Disabling device |
| [DEBUG] PCI: 00:19.0 [8086/1502] enabled |
| [SPEW ] PCI: 00:1a.0 [8086/0000] ops |
| [DEBUG] PCI: 00:1a.0 [8086/1e2d] enabled |
| [SPEW ] PCI: 00:1b.0 [8086/0000] ops |
| [DEBUG] PCI: 00:1b.0 [8086/1e20] enabled |
| [INFO ] PCH: PCIe Root Port coalescing is enabled |
| [SPEW ] PCI: 00:1c.0 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1c.0 [8086/1e10] enabled |
| [SPEW ] PCI: 00:1c.1 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1c.1 [8086/1e12] enabled |
| [SPEW ] PCI: 00:1c.2 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1c.2 [8086/1e14] enabled |
| [DEBUG] PCI: 00:1c.3: Disabling device |
| [SPEW ] PCI: 00:1c.3 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1c.3 [8086/1e16] disabled |
| [DEBUG] PCI: 00:1c.4: Disabling device |
| [DEBUG] PCI: 00:1c.4: check set enabled |
| [DEBUG] PCI: 00:1c.5: Disabling device |
| [DEBUG] PCI: 00:1c.6: Disabling device |
| [DEBUG] PCI: 00:1c.7: Disabling device |
| [SPEW ] PCH: RPFN 0x76543210 -> 0xfedcb210 |
| [SPEW ] PCI: 00:1d.0 [8086/0000] ops |
| [DEBUG] PCI: 00:1d.0 [8086/1e26] enabled |
| [DEBUG] PCI: 00:1e.0: Disabling device |
| [SPEW ] PCI: 00:1e.0 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1e.0 [8086/2448] disabled |
| [SPEW ] PCI: 00:1f.0 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1f.0 [8086/1e55] enabled |
| [SPEW ] PCI: 00:1f.2 [8086/0000] ops |
| [DEBUG] PCI: 00:1f.2 [8086/1e01] enabled |
| [SPEW ] PCI: 00:1f.3 [8086/0000] bus ops |
| [DEBUG] PCI: 00:1f.3 [8086/1e22] enabled |
| [DEBUG] PCI: 00:1f.5: Disabling device |
| [DEBUG] PCI: 00:1f.5 [8086/1e09] disabled No operations |
| [DEBUG] PCI: 00:1f.6 [8086/1e24] enabled |
| [WARN ] PCI: Leftover static devices: |
| [WARN ] PCI: 00:01.1 |
| [WARN ] PCI: 00:01.2 |
| [WARN ] PCI: 00:06.0 |
| [WARN ] PCI: 00:16.1 |
| [WARN ] PCI: 00:16.2 |
| [WARN ] PCI: 00:16.3 |
| [WARN ] PCI: 00:1c.4 |
| [WARN ] PCI: 00:1c.5 |
| [WARN ] PCI: 00:1c.6 |
| [WARN ] PCI: 00:1c.7 |
| [WARN ] PCI: Check your devicetree.cb. |
| [DEBUG] PCI: 00:1c.0 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:1c.0 |
| [DEBUG] PCI: pci_scan_bus for bus 01 |
| [SPEW ] PCI: 01:00.0 [1180/0000] ops |
| [DEBUG] PCI: 01:00.0 [1180/e823] enabled |
| [INFO ] Enabling Common Clock Configuration |
| [INFO ] ASPM: Enabled L0s and L1 |
| [INFO ] PCIe: Max_Payload_Size adjusted to 128 |
| [DEBUG] PCI: 01:00.0: No LTR support |
| [DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs |
| [DEBUG] PCI: 00:1c.1 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:1c.1 |
| [DEBUG] PCI: pci_scan_bus for bus 02 |
| [DEBUG] PCI: 02:00.0 [168c/002a] enabled |
| [INFO ] Enabling Common Clock Configuration |
| [INFO ] ASPM: Enabled L1 |
| [INFO ] PCIe: Max_Payload_Size adjusted to 128 |
| [DEBUG] PCI: 02:00.0: No LTR support |
| [DEBUG] scan_bus: bus PCI: 00:1c.1 finished in 0 msecs |
| [DEBUG] PCI: 00:1c.2 scanning... |
| [SPEW ] do_pci_scan_bridge for PCI: 00:1c.2 |
| [DEBUG] PCI: pci_scan_bus for bus 03 |
| [DEBUG] scan_bus: bus PCI: 00:1c.2 finished in 0 msecs |
| [DEBUG] PCI: 00:1f.0 scanning... |
| [SPEW ] scan_static_bus for PCI: 00:1f.0 |
| [INFO ] PMH7: ID 05 Revision 00 |
| [DEBUG] PNP: 00ff.1 enabled |
| [DEBUG] PNP: 0c31.0 enabled |
| [SPEW ] Clearing EC output queue... |
| [SPEW ] EC output queue has been cleared. |
| [SPEW ] recv_ec_data_timeout: 0x47 |
| [SPEW ] recv_ec_data_timeout: 0x32 |
| [SPEW ] recv_ec_data_timeout: 0x48 |
| [SPEW ] recv_ec_data_timeout: 0x54 |
| [SPEW ] recv_ec_data_timeout: 0x33 |
| [SPEW ] recv_ec_data_timeout: 0x35 |
| [SPEW ] recv_ec_data_timeout: 0x57 |
| [SPEW ] recv_ec_data_timeout: 0x57 |
| [SPEW ] recv_ec_data_timeout: 0x16 |
| [SPEW ] recv_ec_data_timeout: 0x03 |
| [SPEW ] recv_ec_data_timeout: 0x40 |
| [SPEW ] recv_ec_data_timeout: 0x11 |
| [INFO ] H8: EC Firmware ID G2HT35WW-3.22, Version 4.01B |
| [SPEW ] recv_ec_data_timeout: 0x01 |
| [SPEW ] recv_ec_data_timeout: 0x01 |
| [SPEW ] recv_ec_data_timeout: 0x80 |
| [SPEW ] recv_ec_data_timeout: 0x21 |
| [INFO ] H8: WWAN not installed |
| [SPEW ] recv_ec_data_timeout: 0x31 |
| [SPEW ] recv_ec_data_timeout: 0x00 |
| [SPEW ] recv_ec_data_timeout: 0xa6 |
| [SPEW ] recv_ec_data_timeout: 0xa6 |
| [SPEW ] recv_ec_data_timeout: 0x31 |
| [DEBUG] PNP: 00ff.2 enabled |
| [SPEW ] scan_static_bus for PCI: 00:1f.0 done |
| [DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 3 msecs |
| [DEBUG] PCI: 00:1f.3 scanning... |
| [SPEW ] scan_generic_bus for PCI: 00:1f.3 |
| [DEBUG] I2C: 01:54 enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->scan_generic_bus for PCI: 00:1f.3 done |
| [DEBUG] scan_bus: bus PCI: 00:1f.3 finished in 0 msecs |
| [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 3 msecs |
| [SPEW ] scan_static_bus for Root Device done |
| [DEBUG] scan_bus: bus Root Device finished in 3 msecs |
| [INFO ] done |
| [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 4 / 0 ms |
| [DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes) |
| [DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes) |
| [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'. |
| [DEBUG] flash size 0xc00000 bytes |
| [INFO ] SF: Detected 00 0000 with sector size 0x100, total 0xc00000 |
| [DEBUG] MRC: 'RW_MRC_CACHE' does not need update. |
| [DEBUG] found VGA at PCI: 00:02.0 |
| [DEBUG] Setting up VGA for PCI: 00:02.0 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| [INFO ] Allocating resources... |
| [INFO ] Reading resources... |
| [SPEW ] Root Device read_resources bus 0 link: 0 |
| [SPEW ] DOMAIN: 0000 read_resources bus 0 link: 0 |
| [DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| [DEBUG] TOUUD 0x47d600000 TOLUD 0x82a00000 TOM 0x400000000 |
| [DEBUG] MEBASE 0x7ffff00000 |
| [DEBUG] IGD decoded, subtracting 32M UMA and 2M GTT |
| [DEBUG] TSEG base 0x80000000 size 8M |
| [INFO ] Available memory below 4GB: 2048M |
| [SPEW ] dev: PCI: 00:00.0, index: 0x3, base: 0x0, size: 0xa0000 |
| [SPEW ] dev: PCI: 00:00.0, index: 0x4, base: 0x100000, size: 0x7ff00000 |
| [INFO ] Available memory above 4GB: 14294M |
| [SPEW ] dev: PCI: 00:00.0, index: 0x5, base: 0x100000000, size: 0x37d600000 |
| [SPEW ] dev: PCI: 00:00.0, index: 0x6, base: 0x80000000, size: 0x2a00000 |
| [SPEW ] dev: PCI: 00:00.0, index: 0x7, base: 0xa0000, size: 0x20000 |
| [SPEW ] dev: PCI: 00:00.0, index: 0x8, base: 0xc0000, size: 0x40000 |
| [SPEW ] dev: PCI: 00:00.0, index: 0x9, base: 0xfed90000, size: 0x1000 |
| [SPEW ] dev: PCI: 00:00.0, index: 0xa, base: 0xfed91000, size: 0x1000 |
| [SPEW ] PCI: 00:1c.0 read_resources bus 1 link: 0 |
| [SPEW ] PCI: 00:1c.0 read_resources bus 1 link: 0 done |
| [SPEW ] PCI: 00:1c.1 read_resources bus 2 link: 0 |
| [SPEW ] PCI: 00:1c.1 read_resources bus 2 link: 0 done |
| [SPEW ] PCI: 00:1c.2 read_resources bus 3 link: 0 |
| [SPEW ] PCI: 00:1c.2 read_resources bus 3 link: 0 done |
| [SPEW ] PCI: 00:1f.0 read_resources bus 0 link: 0 |
| [ERROR] PNP: 00ff.1 missing read_resources |
| [SPEW ] dev: PNP: 0c31.0, index: 0x0, base: 0xfed40000, size: 0x5000 |
| [ERROR] PNP: 00ff.2 missing read_resources |
| [SPEW ] PCI: 00:1f.0 read_resources bus 0 link: 0 done |
| [SPEW ] PCI: 00:1f.3 read_resources bus 1 link: 0 |
| [SPEW ] PCI: 00:1f.3 read_resources bus 1 link: 0 done |
| [SPEW ] DOMAIN: 0000 read_resources bus 0 link: 0 done |
| [SPEW ] Root Device read_resources bus 0 link: 0 done |
| [INFO ] Done reading resources. |
| [SPEW ] Show resources in subtree (Root Device)...After reading. |
| [DEBUG] Root Device child on link 0 CPU_CLUSTER: 0 |
| [DEBUG] CPU_CLUSTER: 0 |
| [DEBUG] DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| [SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| [SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit fffffffff flags 40040200 index 10000100 |
| [DEBUG] PCI: 00:00.0 |
| [SPEW ] PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| [SPEW ] PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| [SPEW ] PCI: 00:00.0 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| [SPEW ] PCI: 00:00.0 resource base 100000000 size 37d600000 align 0 gran 0 limit 0 flags e0004200 index 5 |
| [SPEW ] PCI: 00:00.0 resource base 80000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| [SPEW ] PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| [SPEW ] PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8 |
| [SPEW ] PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9 |
| [SPEW ] PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a |
| [DEBUG] PCI: 00:01.0 |
| [DEBUG] PCI: 00:02.0 |
| [SPEW ] PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 |
| [SPEW ] PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 |
| [SPEW ] PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 |
| [DEBUG] PCI: 00:04.0 |
| [DEBUG] PCI: 00:14.0 |
| [SPEW ] PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 |
| [DEBUG] PCI: 00:16.0 |
| [SPEW ] PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10 |
| [DEBUG] PCI: 00:19.0 |
| [SPEW ] PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 |
| [SPEW ] PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 |
| [SPEW ] PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 |
| [DEBUG] PCI: 00:1a.0 |
| [SPEW ] PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| [DEBUG] PCI: 00:1b.0 |
| [SPEW ] PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 |
| [DEBUG] PCI: 00:1c.0 child on link 0 PCI: 01:00.0 |
| [SPEW ] PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] PCI: 01:00.0 |
| [SPEW ] PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 |
| [DEBUG] PCI: 00:1c.1 child on link 0 PCI: 02:00.0 |
| [SPEW ] PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] PCI: 02:00.0 |
| [SPEW ] PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 |
| [DEBUG] PCI: 00:1c.2 child on link 0 NONE |
| [SPEW ] PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c |
| [SPEW ] PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 |
| [SPEW ] PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 |
| [DEBUG] NONE |
| [SPEW ] NONE resource base 0 size 800000 align 12 gran 12 limit ffffffff flags 200 index 10 |
| [SPEW ] NONE resource base 0 size 10000000 align 12 gran 12 limit ffffffffffffffff flags 101200 index 14 |
| [SPEW ] NONE resource base 0 size 2000 align 12 gran 12 limit ffff flags 100 index 18 |
| [DEBUG] PCI: 00:1c.3 |
| [DEBUG] PCI: 00:1d.0 |
| [SPEW ] PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 |
| [DEBUG] PCI: 00:1e.0 |
| [DEBUG] PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| [SPEW ] PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| [SPEW ] PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| [SPEW ] PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| [SPEW ] PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| [SPEW ] PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 |
| [DEBUG] PNP: 00ff.1 |
| [SPEW ] PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags c0000100 index 77 |
| [DEBUG] PNP: 0c31.0 |
| [SPEW ] PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| [SPEW ] PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| [DEBUG] PNP: 00ff.2 |
| [SPEW ] PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| [SPEW ] PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| [SPEW ] PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| [SPEW ] PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| [DEBUG] PCI: 00:1f.2 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 |
| [SPEW ] PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 |
| [DEBUG] PCI: 00:1f.3 child on link 0 I2C: 01:54 |
| [SPEW ] PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 |
| [SPEW ] PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| [DEBUG] I2C: 01:54 |
| [DEBUG] I2C: 01:55 |
| [DEBUG] I2C: 01:56 |
| [DEBUG] I2C: 01:57 |
| [DEBUG] I2C: 01:5c |
| [DEBUG] I2C: 01:5d |
| [DEBUG] I2C: 01:5e |
| [DEBUG] I2C: 01:5f |
| [DEBUG] PCI: 00:1f.5 |
| [DEBUG] PCI: 00:1f.6 |
| [SPEW ] PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 |
| [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === |
| [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 01:00.0 10 * [0x0 - 0xff] mem |
| [DEBUG] PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| [DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 02:00.0 10 * [0x0 - 0xffff] mem |
| [DEBUG] PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| [DEBUG] PCI: 00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] NONE 18 * [0x0 - 0x1fff] io |
| [DEBUG] PCI: 00:1c.2 io: size: 2000 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:1c.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] NONE 10 * [0x0 - 0x7fffff] mem |
| [DEBUG] PCI: 00:1c.2 mem: size: 800000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] NONE 14 * [0x0 - 0xfffffff] prefmem |
| [DEBUG] PCI: 00:1c.2 prefmem: size: 10000000 align: 20 gran: 20 limit: ffffffffffffffff done |
| [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === |
| [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000300 base 000015e0 limit 000015eb io (fixed) |
| [DEBUG] update_constraints: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed) |
| [INFO ] DOMAIN: 0000: Resource ranges: |
| [INFO ] * Base: 1000, Size: 5e0, Tag: 100 |
| [INFO ] * Base: 15f0, Size: 10, Tag: 100 |
| [INFO ] * Base: 167c, Size: e984, Tag: 100 |
| [DEBUG] PCI: 00:1c.2 1c * [0x2000 - 0x3fff] limit: 3fff io |
| [DEBUG] PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io |
| [DEBUG] PCI: 00:19.0 18 * [0x1040 - 0x105f] limit: 105f io |
| [DEBUG] PCI: 00:1f.2 20 * [0x1060 - 0x107f] limit: 107f io |
| [DEBUG] PCI: 00:1f.2 10 * [0x1080 - 0x1087] limit: 1087 io |
| [DEBUG] PCI: 00:1f.2 18 * [0x1088 - 0x108f] limit: 108f io |
| [DEBUG] PCI: 00:1f.2 14 * [0x1090 - 0x1093] limit: 1093 io |
| [DEBUG] PCI: 00:1f.2 1c * [0x1094 - 0x1097] limit: 1097 io |
| [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done |
| [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff |
| [DEBUG] update_constraints: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 03 base 00000000 limit 0009ffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 04 base 00100000 limit 7fffffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 05 base 100000000 limit 47d5fffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 06 base 80000000 limit 829fffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 07 base 000a0000 limit 000bffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 08 base 000c0000 limit 000fffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 09 base fed90000 limit fed90fff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 0a base fed91000 limit fed91fff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed) |
| [DEBUG] update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed) |
| [INFO ] DOMAIN: 0000: Resource ranges: |
| [INFO ] * Base: 82a00000, Size: 6d600000, Tag: 200 |
| [INFO ] * Base: f4000000, Size: ac00000, Tag: 200 |
| [INFO ] * Base: fec01000, Size: 13f000, Tag: 200 |
| [INFO ] * Base: fed45000, Size: 4b000, Tag: 200 |
| [INFO ] * Base: fed92000, Size: 26e000, Tag: 200 |
| [INFO ] * Base: 47d600000, Size: b82a00000, Tag: 100200 |
| [DEBUG] PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem |
| [DEBUG] PCI: 00:02.0 10 * [0x82c00000 - 0x82ffffff] limit: 82ffffff mem |
| [DEBUG] PCI: 00:1c.2 20 * [0x83000000 - 0x837fffff] limit: 837fffff mem |
| [DEBUG] PCI: 00:1c.0 20 * [0x82a00000 - 0x82afffff] limit: 82afffff mem |
| [DEBUG] PCI: 00:1c.1 20 * [0x82b00000 - 0x82bfffff] limit: 82bfffff mem |
| [DEBUG] PCI: 00:19.0 10 * [0x83800000 - 0x8381ffff] limit: 8381ffff mem |
| [DEBUG] PCI: 00:14.0 10 * [0x83820000 - 0x8382ffff] limit: 8382ffff mem |
| [DEBUG] PCI: 00:1b.0 10 * [0x83830000 - 0x83833fff] limit: 83833fff mem |
| [DEBUG] PCI: 00:19.0 14 * [0x83834000 - 0x83834fff] limit: 83834fff mem |
| [DEBUG] PCI: 00:1f.6 10 * [0x83835000 - 0x83835fff] limit: 83835fff mem |
| [DEBUG] PCI: 00:1f.2 24 * [0x83836000 - 0x838367ff] limit: 838367ff mem |
| [DEBUG] PCI: 00:1a.0 10 * [0x83837000 - 0x838373ff] limit: 838373ff mem |
| [DEBUG] PCI: 00:1d.0 10 * [0x83838000 - 0x838383ff] limit: 838383ff mem |
| [DEBUG] PCI: 00:1f.3 10 * [0x83839000 - 0x838390ff] limit: 838390ff mem |
| [DEBUG] PCI: 00:16.0 10 * [0x8383a000 - 0x8383a00f] limit: 8383a00f mem |
| [DEBUG] PCI: 00:1c.2 24 * [0x47d600000 - 0x48d5fffff] limit: 48d5fffff prefmem |
| [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done |
| [DEBUG] PCI: 00:1c.0 mem: base: 82a00000 size: 100000 align: 20 gran: 20 limit: 82afffff |
| [INFO ] PCI: 00:1c.0: Resource ranges: |
| [INFO ] * Base: 82a00000, Size: 100000, Tag: 200 |
| [DEBUG] PCI: 01:00.0 10 * [0x82a00000 - 0x82a000ff] limit: 82a000ff mem |
| [DEBUG] PCI: 00:1c.0 mem: base: 82a00000 size: 100000 align: 20 gran: 20 limit: 82afffff done |
| [DEBUG] PCI: 00:1c.1 mem: base: 82b00000 size: 100000 align: 20 gran: 20 limit: 82bfffff |
| [INFO ] PCI: 00:1c.1: Resource ranges: |
| [INFO ] * Base: 82b00000, Size: 100000, Tag: 200 |
| [DEBUG] PCI: 02:00.0 10 * [0x82b00000 - 0x82b0ffff] limit: 82b0ffff mem |
| [DEBUG] PCI: 00:1c.1 mem: base: 82b00000 size: 100000 align: 20 gran: 20 limit: 82bfffff done |
| [DEBUG] PCI: 00:1c.2 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff |
| [INFO ] PCI: 00:1c.2: Resource ranges: |
| [INFO ] * Base: 2000, Size: 2000, Tag: 100 |
| [DEBUG] NONE 18 * [0x2000 - 0x3fff] limit: 3fff io |
| [DEBUG] PCI: 00:1c.2 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff done |
| [DEBUG] PCI: 00:1c.2 prefmem: base: 47d600000 size: 10000000 align: 20 gran: 20 limit: 48d5fffff |
| [INFO ] PCI: 00:1c.2: Resource ranges: |
| [INFO ] * Base: 47d600000, Size: 10000000, Tag: 1200 |
| [DEBUG] NONE 14 * [0x47d600000 - 0x48d5fffff] limit: 48d5fffff prefmem |
| [DEBUG] PCI: 00:1c.2 prefmem: base: 47d600000 size: 10000000 align: 20 gran: 20 limit: 48d5fffff done |
| [DEBUG] PCI: 00:1c.2 mem: base: 83000000 size: 800000 align: 20 gran: 20 limit: 837fffff |
| [INFO ] PCI: 00:1c.2: Resource ranges: |
| [INFO ] * Base: 83000000, Size: 800000, Tag: 200 |
| [DEBUG] NONE 10 * [0x83000000 - 0x837fffff] limit: 837fffff mem |
| [DEBUG] PCI: 00:1c.2 mem: base: 83000000 size: 800000 align: 20 gran: 20 limit: 837fffff done |
| [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete === |
| [SPEW ] Root Device assign_resources, bus 0 link: 0 |
| [SPEW ] DOMAIN: 0000 assign_resources, bus 0 link: 0 |
| [DEBUG] PCI: 00:02.0 10 <- [0x0000000082c00000 - 0x0000000082ffffff] size 0x00400000 gran 0x16 mem64 |
| [DEBUG] PCI: 00:02.0 18 <- [0x0000000090000000 - 0x000000009fffffff] size 0x10000000 gran 0x1c prefmem64 |
| [DEBUG] PCI: 00:02.0 20 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io |
| [DEBUG] PCI: 00:14.0 10 <- [0x0000000083820000 - 0x000000008382ffff] size 0x00010000 gran 0x10 mem64 |
| [DEBUG] PCI: 00:16.0 10 <- [0x000000008383a000 - 0x000000008383a00f] size 0x00000010 gran 0x04 mem64 |
| [DEBUG] PCI: 00:19.0 10 <- [0x0000000083800000 - 0x000000008381ffff] size 0x00020000 gran 0x11 mem |
| [DEBUG] PCI: 00:19.0 14 <- [0x0000000083834000 - 0x0000000083834fff] size 0x00001000 gran 0x0c mem |
| [DEBUG] PCI: 00:19.0 18 <- [0x0000000000001040 - 0x000000000000105f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1a.0 10 <- [0x0000000083837000 - 0x00000000838373ff] size 0x00000400 gran 0x0a mem |
| [DEBUG] PCI: 00:1b.0 10 <- [0x0000000083830000 - 0x0000000083833fff] size 0x00004000 gran 0x0e mem64 |
| [DEBUG] PCI: 00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| [DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| [DEBUG] PCI: 00:1c.0 20 <- [0x0000000082a00000 - 0x0000000082afffff] size 0x00100000 gran 0x14 bus 01 mem |
| [SPEW ] PCI: 00:1c.0 assign_resources, bus 1 link: 0 |
| [DEBUG] PCI: 01:00.0 10 <- [0x0000000082a00000 - 0x0000000082a000ff] size 0x00000100 gran 0x08 mem |
| [SPEW ] PCI: 00:1c.0 assign_resources, bus 1 link: 0 done |
| [DEBUG] PCI: 00:1c.1 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| [DEBUG] PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| [DEBUG] PCI: 00:1c.1 20 <- [0x0000000082b00000 - 0x0000000082bfffff] size 0x00100000 gran 0x14 bus 02 mem |
| [SPEW ] PCI: 00:1c.1 assign_resources, bus 2 link: 0 |
| [DEBUG] PCI: 02:00.0 10 <- [0x0000000082b00000 - 0x0000000082b0ffff] size 0x00010000 gran 0x10 mem64 |
| [SPEW ] PCI: 00:1c.1 assign_resources, bus 2 link: 0 done |
| [DEBUG] PCI: 00:1c.2 1c <- [0x0000000000002000 - 0x0000000000003fff] size 0x00002000 gran 0x0c bus 03 io |
| [DEBUG] PCI: 00:1c.2 24 <- [0x000000047d600000 - 0x000000048d5fffff] size 0x10000000 gran 0x14 bus 03 prefmem |
| [DEBUG] PCI: 00:1c.2 20 <- [0x0000000083000000 - 0x00000000837fffff] size 0x00800000 gran 0x14 bus 03 mem |
| [SPEW ] PCI: 00:1c.2 assign_resources, bus 3 link: 0 |
| [SPEW ] PCI: 00:1c.2 assign_resources, bus 3 link: 0 done |
| [DEBUG] PCI: 00:1d.0 10 <- [0x0000000083838000 - 0x00000000838383ff] size 0x00000400 gran 0x0a mem |
| [SPEW ] PCI: 00:1f.0 assign_resources, bus 0 link: 0 |
| [ERROR] PNP: 00ff.1 missing set_resources |
| [ERROR] PNP: 00ff.2 missing set_resources |
| [SPEW ] PCI: 00:1f.0 assign_resources, bus 0 link: 0 done |
| [DEBUG] PCI: 00:1f.2 10 <- [0x0000000000001080 - 0x0000000000001087] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:1f.2 14 <- [0x0000000000001090 - 0x0000000000001093] size 0x00000004 gran 0x02 io |
| [DEBUG] PCI: 00:1f.2 18 <- [0x0000000000001088 - 0x000000000000108f] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:1f.2 1c <- [0x0000000000001094 - 0x0000000000001097] size 0x00000004 gran 0x02 io |
| [DEBUG] PCI: 00:1f.2 20 <- [0x0000000000001060 - 0x000000000000107f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1f.2 24 <- [0x0000000083836000 - 0x00000000838367ff] size 0x00000800 gran 0x0b mem |
| [DEBUG] PCI: 00:1f.3 10 <- [0x0000000083839000 - 0x00000000838390ff] size 0x00000100 gran 0x08 mem64 |
| [SPEW ] PCI: 00:1f.3 assign_resources, bus 1 link: 0 |
| [SPEW ] PCI: 00:1f.3 assign_resources, bus 1 link: 0 done |
| [DEBUG] PCI: 00:1f.6 10 <- [0x0000000083835000 - 0x0000000083835fff] size 0x00001000 gran 0x0c mem64 |
| [SPEW ] DOMAIN: 0000 assign_resources, bus 0 link: 0 done |
| [SPEW ] Root Device assign_resources, bus 0 link: 0 done |
| [INFO ] Done setting resources. |
| [SPEW ] Show resources in subtree (Root Device)...After assigning values. |
| [DEBUG] Root Device child on link 0 CPU_CLUSTER: 0 |
| [DEBUG] CPU_CLUSTER: 0 |
| [DEBUG] DOMAIN: 0000 child on link 0 PCI: 00:00.0 |
| [SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 |
| [SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit fffffffff flags 40040200 index 10000100 |
| [DEBUG] PCI: 00:00.0 |
| [SPEW ] PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 |
| [SPEW ] PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 |
| [SPEW ] PCI: 00:00.0 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4 |
| [SPEW ] PCI: 00:00.0 resource base 100000000 size 37d600000 align 0 gran 0 limit 0 flags e0004200 index 5 |
| [SPEW ] PCI: 00:00.0 resource base 80000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 |
| [SPEW ] PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 |
| [SPEW ] PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8 |
| [SPEW ] PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9 |
| [SPEW ] PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a |
| [DEBUG] PCI: 00:01.0 |
| [DEBUG] PCI: 00:02.0 |
| [SPEW ] PCI: 00:02.0 resource base 82c00000 size 400000 align 22 gran 22 limit 82ffffff flags 60000201 index 10 |
| [SPEW ] PCI: 00:02.0 resource base 90000000 size 10000000 align 28 gran 28 limit 9fffffff flags 60001201 index 18 |
| [SPEW ] PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20 |
| [DEBUG] PCI: 00:04.0 |
| [DEBUG] PCI: 00:14.0 |
| [SPEW ] PCI: 00:14.0 resource base 83820000 size 10000 align 16 gran 16 limit 8382ffff flags 60000201 index 10 |
| [DEBUG] PCI: 00:16.0 |
| [SPEW ] PCI: 00:16.0 resource base 8383a000 size 10 align 12 gran 4 limit 8383a00f flags 60000201 index 10 |
| [DEBUG] PCI: 00:19.0 |
| [SPEW ] PCI: 00:19.0 resource base 83800000 size 20000 align 17 gran 17 limit 8381ffff flags 60000200 index 10 |
| [SPEW ] PCI: 00:19.0 resource base 83834000 size 1000 align 12 gran 12 limit 83834fff flags 60000200 index 14 |
| [SPEW ] PCI: 00:19.0 resource base 1040 size 20 align 5 gran 5 limit 105f flags 60000100 index 18 |
| [DEBUG] PCI: 00:1a.0 |
| [SPEW ] PCI: 00:1a.0 resource base 83837000 size 400 align 12 gran 10 limit 838373ff flags 60000200 index 10 |
| [DEBUG] PCI: 00:1b.0 |
| [SPEW ] PCI: 00:1b.0 resource base 83830000 size 4000 align 14 gran 14 limit 83833fff flags 60000201 index 10 |
| [DEBUG] PCI: 00:1c.0 child on link 0 PCI: 01:00.0 |
| [SPEW ] PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c |
| [SPEW ] PCI: 00:1c.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| [SPEW ] PCI: 00:1c.0 resource base 82a00000 size 100000 align 20 gran 20 limit 82afffff flags 60080202 index 20 |
| [DEBUG] PCI: 01:00.0 |
| [SPEW ] PCI: 01:00.0 resource base 82a00000 size 100 align 12 gran 8 limit 82a000ff flags 60000200 index 10 |
| [DEBUG] PCI: 00:1c.1 child on link 0 PCI: 02:00.0 |
| [SPEW ] PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c |
| [SPEW ] PCI: 00:1c.1 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 |
| [SPEW ] PCI: 00:1c.1 resource base 82b00000 size 100000 align 20 gran 20 limit 82bfffff flags 60080202 index 20 |
| [DEBUG] PCI: 02:00.0 |
| [SPEW ] PCI: 02:00.0 resource base 82b00000 size 10000 align 16 gran 16 limit 82b0ffff flags 60000201 index 10 |
| [DEBUG] PCI: 00:1c.2 child on link 0 NONE |
| [SPEW ] PCI: 00:1c.2 resource base 2000 size 2000 align 12 gran 12 limit 3fff flags 60080102 index 1c |
| [SPEW ] PCI: 00:1c.2 resource base 47d600000 size 10000000 align 20 gran 20 limit 48d5fffff flags 60181202 index 24 |
| [SPEW ] PCI: 00:1c.2 resource base 83000000 size 800000 align 20 gran 20 limit 837fffff flags 60080202 index 20 |
| [DEBUG] NONE |
| [SPEW ] NONE resource base 83000000 size 800000 align 12 gran 12 limit 837fffff flags 40000200 index 10 |
| [SPEW ] NONE resource base 47d600000 size 10000000 align 12 gran 12 limit 48d5fffff flags 40101200 index 14 |
| [SPEW ] NONE resource base 2000 size 2000 align 12 gran 12 limit 3fff flags 40000100 index 18 |
| [DEBUG] PCI: 00:1c.3 |
| [DEBUG] PCI: 00:1d.0 |
| [SPEW ] PCI: 00:1d.0 resource base 83838000 size 400 align 12 gran 10 limit 838383ff flags 60000200 index 10 |
| [DEBUG] PCI: 00:1e.0 |
| [DEBUG] PCI: 00:1f.0 child on link 0 PNP: 00ff.1 |
| [SPEW ] PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 |
| [SPEW ] PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 |
| [SPEW ] PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 |
| [SPEW ] PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200 |
| [SPEW ] PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300 |
| [DEBUG] PNP: 00ff.1 |
| [SPEW ] PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags c0000100 index 77 |
| [DEBUG] PNP: 0c31.0 |
| [SPEW ] PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 |
| [SPEW ] PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0 |
| [DEBUG] PNP: 00ff.2 |
| [SPEW ] PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 |
| [SPEW ] PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 |
| [SPEW ] PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 |
| [SPEW ] PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 |
| [DEBUG] PCI: 00:1f.2 |
| [SPEW ] PCI: 00:1f.2 resource base 1080 size 8 align 3 gran 3 limit 1087 flags 60000100 index 10 |
| [SPEW ] PCI: 00:1f.2 resource base 1090 size 4 align 2 gran 2 limit 1093 flags 60000100 index 14 |
| [SPEW ] PCI: 00:1f.2 resource base 1088 size 8 align 3 gran 3 limit 108f flags 60000100 index 18 |
| [SPEW ] PCI: 00:1f.2 resource base 1094 size 4 align 2 gran 2 limit 1097 flags 60000100 index 1c |
| [SPEW ] PCI: 00:1f.2 resource base 1060 size 20 align 5 gran 5 limit 107f flags 60000100 index 20 |
| [SPEW ] PCI: 00:1f.2 resource base 83836000 size 800 align 12 gran 11 limit 838367ff flags 60000200 index 24 |
| [DEBUG] PCI: 00:1f.3 child on link 0 I2C: 01:54 |
| [SPEW ] PCI: 00:1f.3 resource base 83839000 size 100 align 12 gran 8 limit 838390ff flags 60000201 index 10 |
| [SPEW ] PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 |
| [DEBUG] I2C: 01:54 |
| [DEBUG] I2C: 01:55 |
| [DEBUG] I2C: 01:56 |
| [DEBUG] I2C: 01:57 |
| [DEBUG] I2C: 01:5c |
| [DEBUG] I2C: 01:5d |
| [DEBUG] I2C: 01:5e |
| [DEBUG] I2C: 01:5f |
| [DEBUG] PCI: 00:1f.5 |
| [DEBUG] PCI: 00:1f.6 |
| [SPEW ] PCI: 00:1f.6 resource base 83835000 size 1000 align 12 gran 12 limit 83835fff flags 60000201 index 10 |
| [INFO ] Done allocating resources. |
| [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 1 ms |
| [INFO ] Enabling resources... |
| [DEBUG] PCI: 00:00.0 subsystem <- 8086/0154 |
| [DEBUG] PCI: 00:00.0 cmd <- 06 |
| [DEBUG] PCI: 00:02.0 subsystem <- 8086/0166 |
| [DEBUG] PCI: 00:02.0 cmd <- 03 |
| [DEBUG] PCI: 00:14.0 subsystem <- 8086/1e31 |
| [DEBUG] PCI: 00:14.0 cmd <- 102 |
| [DEBUG] PCI: 00:16.0 subsystem <- 8086/1e3a |
| [DEBUG] PCI: 00:16.0 cmd <- 02 |
| [DEBUG] PCI: 00:19.0 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:19.0 cmd <- 103 |
| [DEBUG] PCI: 00:1a.0 subsystem <- 8086/1e2d |
| [DEBUG] PCI: 00:1a.0 cmd <- 102 |
| [DEBUG] PCI: 00:1b.0 subsystem <- 8086/1e20 |
| [DEBUG] PCI: 00:1b.0 cmd <- 102 |
| [DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.0 subsystem <- 8086/1e10 |
| [DEBUG] PCI: 00:1c.0 cmd <- 106 |
| [DEBUG] PCI: 00:1c.1 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.1 subsystem <- 8086/1e12 |
| [DEBUG] PCI: 00:1c.1 cmd <- 106 |
| [DEBUG] PCI: 00:1c.2 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.2 subsystem <- 8086/1e14 |
| [DEBUG] PCI: 00:1c.2 cmd <- 107 |
| [DEBUG] PCI: 00:1d.0 subsystem <- 8086/1e26 |
| [DEBUG] PCI: 00:1d.0 cmd <- 102 |
| [DEBUG] PCI: 00:1f.0 subsystem <- 8086/1e55 |
| [DEBUG] PCI: 00:1f.0 cmd <- 107 |
| [DEBUG] PCI: 00:1f.2 subsystem <- 8086/1e03 |
| [DEBUG] PCI: 00:1f.2 cmd <- 03 |
| [DEBUG] PCI: 00:1f.3 subsystem <- 8086/1e22 |
| [DEBUG] PCI: 00:1f.3 cmd <- 103 |
| [DEBUG] PCI: 00:1f.6 subsystem <- 8086/1e24 |
| [DEBUG] PCI: 00:1f.6 cmd <- 02 |
| [DEBUG] PCI: 01:00.0 subsystem <- 1180/e823 |
| [DEBUG] PCI: 01:00.0 cmd <- 06 |
| [DEBUG] PCI: 02:00.0 cmd <- 02 |
| [INFO ] done. |
| [INFO ] Initializing devices... |
| [DEBUG] CPU_CLUSTER: 0 init |
| [DEBUG] MTRR: Physical address space: |
| [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 |
| [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 |
| [DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6 |
| [DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 0 |
| [DEBUG] 0x0000000090000000 - 0x000000009fffffff size 0x10000000 type 1 |
| [DEBUG] 0x00000000a0000000 - 0x00000000ffffffff size 0x60000000 type 0 |
| [DEBUG] 0x0000000100000000 - 0x000000047d5fffff size 0x37d600000 type 6 |
| [DEBUG] 0x000000047d600000 - 0x000000048d5fffff size 0x10000000 type 0 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| [SPEW ] apic_id 0x0 call enable_fixed_mtrr() |
| [DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 36 bits |
| [DEBUG] MTRR: default type WB/UC MTRR counts: 12/8. |
| [DEBUG] MTRR: UC selected as default type. |
| [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 |
| [DEBUG] MTRR: 1 base 0x0000000090000000 mask 0x0000000ff0000000 type 1 |
| [DEBUG] MTRR: 2 base 0x0000000100000000 mask 0x0000000f00000000 type 6 |
| [DEBUG] MTRR: 3 base 0x0000000200000000 mask 0x0000000e00000000 type 6 |
| [DEBUG] MTRR: 4 base 0x0000000400000000 mask 0x0000000f80000000 type 6 |
| [DEBUG] MTRR: 5 base 0x000000047d600000 mask 0x0000000fffe00000 type 0 |
| [DEBUG] MTRR: 6 base 0x000000047d800000 mask 0x0000000fff800000 type 0 |
| [DEBUG] MTRR: 7 base 0x000000047e000000 mask 0x0000000ffe000000 type 0 |
| |
| [DEBUG] MTRR check |
| [DEBUG] Fixed MTRRs : Enabled |
| [DEBUG] Variable MTRRs: Enabled |
| |
| [DEBUG] CPU has 2 cores, 4 threads enabled. |
| [DEBUG] Setting up SMI for CPU |
| [INFO ] Will perform SMM setup. |
| [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x13940 size 0x6800 in mcache @0x7ffdd0ac |
| [DEBUG] microcode: sig=0x306a9 pf=0x10 revision=0x21 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz. |
| [INFO ] LAPIC 0x0 in XAPIC mode. |
| [DEBUG] CPU: APIC: 00 enabled |
| [DEBUG] CPU: APIC: 01 enabled |
| [DEBUG] CPU: APIC: 02 enabled |
| [DEBUG] CPU: APIC: 03 enabled |
| [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 |
| [DEBUG] Processing 16 relocs. Offset value of 0x00030000 |
| [DEBUG] Attempting to start 3 APs |
| [DEBUG] Waiting for 10ms after sending INIT. |
| [DEBUG] Waiting for SIPI to complete... |
| [DEBUG] done. |
| [SPEW ] APs are ready after 15us |
| [INFO ] LAPIC 0x1 in XAPIC mode. |
| [DEBUG] Waiting for SIPI to complete... |
| [DEBUG] done. |
| [SPEW ] APs are ready after 0us |
| [INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000021 |
| [INFO ] LAPIC 0x3 in XAPIC mode. |
| [INFO ] LAPIC 0x2 in XAPIC mode. |
| [INFO ] AP: slot 2 apic_id 3, MCU rev: 0x00000021 |
| [INFO ] AP: slot 3 apic_id 2, MCU rev: 0x00000021 |
| [SPEW ] APs are ready after 6800us |
| [SPEW ] smm_setup_relocation_handler: enter |
| [SPEW ] smm_setup_relocation_handler: exit |
| [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e8 memsize: 0x1e8 |
| [DEBUG] Processing 11 relocs. Offset value of 0x00038000 |
| [DEBUG] smm_module_setup_stub: stack_top = 0x80001000 |
| [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 |
| [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c |
| [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000 |
| [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7ff99768 |
| [DEBUG] Installing permanent SMM handler to 0x80000000 |
| [DEBUG] FX_SAVE [0x802ff800-0x80300000] |
| [DEBUG] HANDLER [0x802fd000-0x802ff070] |
| |
| [DEBUG] CPU 0 |
| [DEBUG] ss0 [0x802fcc00-0x802fd000] |
| [DEBUG] stub0 [0x802f5000-0x802f51e8] |
| |
| [DEBUG] CPU 1 |
| [DEBUG] ss1 [0x802fc800-0x802fcc00] |
| [DEBUG] stub1 [0x802f4c00-0x802f4de8] |
| |
| [DEBUG] CPU 2 |
| [DEBUG] ss2 [0x802fc400-0x802fc800] |
| [DEBUG] stub2 [0x802f4800-0x802f49e8] |
| |
| [DEBUG] CPU 3 |
| [DEBUG] ss3 [0x802fc000-0x802fc400] |
| [DEBUG] stub3 [0x802f4400-0x802f45e8] |
| |
| [DEBUG] stacks [0x80000000-0x80001000] |
| [DEBUG] Loading module at 0x802fd000 with entry 0x802fd7cd. filesize: 0x2028 memsize: 0x2070 |
| [DEBUG] Processing 93 relocs. Offset value of 0x802fd000 |
| [DEBUG] Loading module at 0x802f5000 with entry 0x802f5000. filesize: 0x1e8 memsize: 0x1e8 |
| [DEBUG] Processing 11 relocs. Offset value of 0x802f5000 |
| [DEBUG] smm_module_setup_stub: stack_top = 0x80001000 |
| [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 |
| [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c |
| [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000 |
| [DEBUG] SMM Module: placing smm entry code at 802f4c00, cpu # 0x1 |
| [SPEW ] smm_place_entry_code: copying from 802f5000 to 802f4c00 0x1e8 bytes |
| [DEBUG] SMM Module: placing smm entry code at 802f4800, cpu # 0x2 |
| [SPEW ] smm_place_entry_code: copying from 802f5000 to 802f4800 0x1e8 bytes |
| [DEBUG] SMM Module: placing smm entry code at 802f4400, cpu # 0x3 |
| [SPEW ] smm_place_entry_code: copying from 802f5000 to 802f4400 0x1e8 bytes |
| [DEBUG] SMM Module: stub loaded at 802f5000. Will call 0x802fd7cd |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed000, cpu = 0 |
| [DEBUG] In relocation handler: cpu 0 |
| [DEBUG] New SMBASE=0x802ed000 IEDBASE=0x80400000 |
| [SPEW ] SMM revision: 0x00030101 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ecc00, cpu = 1 |
| [DEBUG] In relocation handler: cpu 1 |
| [DEBUG] New SMBASE=0x802ecc00 IEDBASE=0x80400000 |
| [SPEW ] SMM revision: 0x00030101 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ec400, cpu = 3 |
| [DEBUG] In relocation handler: cpu 3 |
| [DEBUG] New SMBASE=0x802ec400 IEDBASE=0x80400000 |
| [SPEW ] SMM revision: 0x00030101 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ec800, cpu = 2 |
| [DEBUG] In relocation handler: cpu 2 |
| [DEBUG] New SMBASE=0x802ec800 IEDBASE=0x80400000 |
| [SPEW ] SMM revision: 0x00030101 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [SPEW ] APs are ready after 1100us |
| [INFO ] Initializing CPU #0 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz. |
| [INFO ] CPU: platform id 4 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT supported |
| [INFO ] CPU: VT supported |
| [DEBUG] VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] model_x06ax: frequency set to 2900 |
| [INFO ] Turbo is available but hidden |
| [INFO ] Turbo is available and visible |
| [INFO ] CPU #0 initialized |
| [INFO ] Initializing CPU #1 |
| [INFO ] Initializing CPU #2 |
| [INFO ] Initializing CPU #3 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz. |
| [INFO ] CPU: platform id 4 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz. |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: platform id 4 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz. |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: platform id 4 |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT supported |
| [INFO ] CPU: VT supported |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [DEBUG] VMX status: enabled |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT supported |
| [INFO ] CPU: VT supported |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] VMX status: enabled |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT supported |
| [INFO ] CPU: VT supported |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] model_x06ax: frequency set to 2900 |
| [INFO ] CPU #2 initialized |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] model_x06ax: frequency set to 2900 |
| [INFO ] CPU #3 initialized |
| [DEBUG] model_x06ax: frequency set to 2900 |
| [INFO ] CPU #1 initialized |
| [SPEW ] APs are ready after 100us |
| [INFO ] bsp_do_flight_plan done after 9 msecs. |
| [DEBUG] SMI_STS: |
| [SPEW ] PM1_STS: |
| [SPEW ] PM1_EN: 100 |
| [DEBUG] GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO0 |
| [DEBUG] ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0 |
| [DEBUG] TCO_STS: |
| [DEBUG] Locking SMM. |
| [DEBUG] CPU_CLUSTER: 0 init finished in 23 msecs |
| [DEBUG] PCI: 00:00.0 init |
| [DEBUG] Disabling PEG12. |
| [DEBUG] Disabling PEG11. |
| [DEBUG] Disabling PEG10. |
| [DEBUG] Disabling Device 4. |
| [DEBUG] Disabling PEG60. |
| [DEBUG] Disabling Device 7. |
| [DEBUG] Disabling PEG IO clock. |
| [DEBUG] Set BIOS_RESET_CPL |
| [DEBUG] CPU TDP: 35 Watts |
| [DEBUG] PCI: 00:00.0 init finished in 1 msecs |
| [DEBUG] PCI: 00:02.0 init |
| [DEBUG] GT Power Management Init |
| [DEBUG] IVB GT2 25W-35W Power Meter Weights |
| [DEBUG] GT Power Management Init (post VBIOS) |
| [DEBUG] PCI: 00:02.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:14.0 init |
| [DEBUG] XHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:14.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:16.0 init |
| [NOTE ] ME: BIOS path: S3 Wake |
| [DEBUG] ME: me_state=0, me_state_prev=0 |
| [DEBUG] PCI: 00:16.0: Disabling device |
| [DEBUG] PCI: 00:16.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:19.0 init |
| [DEBUG] PCI: 00:19.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1a.0 init |
| [DEBUG] EHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:1a.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1b.0 init |
| [DEBUG] Azalia: base = 0x83830000 |
| [DEBUG] Azalia: codec_mask = 09 |
| [DEBUG] azalia_audio: Initializing codec #3 |
| [DEBUG] azalia_audio: codec viddid: 80862806 |
| [DEBUG] azalia_audio: verb_size: 16 |
| [DEBUG] azalia_audio: verb loaded. |
| [DEBUG] azalia_audio: Initializing codec #0 |
| [DEBUG] azalia_audio: codec viddid: 10ec0269 |
| [DEBUG] azalia_audio: verb_size: 76 |
| [DEBUG] azalia_audio: verb loaded. |
| [DEBUG] PCI: 00:1b.0 init finished in 5 msecs |
| [DEBUG] PCI: 00:1c.0 init |
| [DEBUG] Initializing PCH PCIe bridge. |
| [DEBUG] PCI: 00:1c.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1c.1 init |
| [DEBUG] Initializing PCH PCIe bridge. |
| [DEBUG] PCI: 00:1c.1 init finished in 0 msecs |
| [DEBUG] PCI: 00:1c.2 init |
| [DEBUG] Initializing PCH PCIe bridge. |
| [DEBUG] PCI: 00:1c.2 init finished in 0 msecs |
| [DEBUG] PCI: 00:1d.0 init |
| [DEBUG] EHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:1d.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1f.0 init |
| [DEBUG] pch: lpc_init |
| [INFO ] PCH: detected QM77, device id: 0x1e55, rev id 0x4 |
| [DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000 |
| [SPEW ] IOAPIC: Dumping registers |
| [SPEW ] reg 0x0000: 0x00000000 |
| [SPEW ] reg 0x0001: 0x00170020 |
| [SPEW ] reg 0x0002: 0x00170020 |
| [DEBUG] IOAPIC: 24 interrupts |
| [DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000 |
| [SPEW ] IOAPIC: vector 0x00 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x01 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x02 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x03 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x04 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x05 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x06 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x07 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x08 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x09 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0a value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0b value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0c value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0d value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0e value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x0f value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x10 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x11 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x12 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x13 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x14 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x15 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x16 value 0x00000000 0x00010000 |
| [SPEW ] IOAPIC: vector 0x17 value 0x00000000 0x00010000 |
| [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| [SPEW ] IOAPIC: vector 0x00 value 0x00000000 0x00000700 |
| [INFO ] Set power off after power failure. |
| [INFO ] NMI sources enabled. |
| [DEBUG] PantherPoint PM init |
| [DEBUG] RTC: failed = 0x0 |
| [DEBUG] pch_spi_init |
| [DEBUG] PCI: 00:1f.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1f.2 init |
| [DEBUG] SATA: Initializing... |
| [DEBUG] SATA: Controller in AHCI mode. |
| [DEBUG] ABAR: 0x83836000 |
| [DEBUG] PCI: 00:1f.2 init finished in 0 msecs |
| [DEBUG] PCI: 00:1f.3 init |
| [DEBUG] PCI: 00:1f.3 init finished in 0 msecs |
| [DEBUG] PCI: 00:1f.6 init |
| [DEBUG] PCI: 00:1f.6 init finished in 0 msecs |
| [DEBUG] PCI: 01:00.0 init |
| [DEBUG] PCI: 01:00.0 init finished in 0 msecs |
| [DEBUG] PCI: 02:00.0 init |
| [DEBUG] PCI: 02:00.0 init finished in 0 msecs |
| [DEBUG] PNP: 00ff.2 init |
| [DEBUG] PNP: 00ff.2 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:54 init |
| [DEBUG] I2C: 01:54 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:55 init |
| [DEBUG] I2C: 01:55 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:56 init |
| [DEBUG] I2C: 01:56 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:57 init |
| [DEBUG] I2C: 01:57 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5c init |
| [DEBUG] Locking EEPROM RFID |
| [DEBUG] init EEPROM done |
| [DEBUG] I2C: 01:5c init finished in 26 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5d init |
| [DEBUG] I2C: 01:5d init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5e init |
| [DEBUG] I2C: 01:5e init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5f init |
| [DEBUG] I2C: 01:5f init finished in 0 msecs |
| [INFO ] Devices initialized |
| [SPEW ] Show all devs... After init. |
| [SPEW ] Root Device: enabled 1 |
| [SPEW ] CPU_CLUSTER: 0: enabled 1 |
| [SPEW ] DOMAIN: 0000: enabled 1 |
| [SPEW ] PCI: 00:00.0: enabled 1 |
| [SPEW ] PCI: 00:01.0: enabled 0 |
| [SPEW ] PCI: 00:01.1: enabled 0 |
| [SPEW ] PCI: 00:01.2: enabled 0 |
| [SPEW ] PCI: 00:02.0: enabled 1 |
| [SPEW ] PCI: 00:04.0: enabled 0 |
| [SPEW ] PCI: 00:06.0: enabled 0 |
| [SPEW ] PCI: 00:14.0: enabled 1 |
| [SPEW ] PCI: 00:16.0: enabled 0 |
| [SPEW ] PCI: 00:16.1: enabled 0 |
| [SPEW ] PCI: 00:16.2: enabled 0 |
| [SPEW ] PCI: 00:16.3: enabled 0 |
| [SPEW ] PCI: 00:19.0: enabled 1 |
| [SPEW ] PCI: 00:1a.0: enabled 1 |
| [SPEW ] PCI: 00:1b.0: enabled 1 |
| [SPEW ] PCI: 00:1c.0: enabled 1 |
| [SPEW ] PCI: 00:1c.1: enabled 1 |
| [SPEW ] PCI: 00:1c.2: enabled 1 |
| [SPEW ] PCI: 00:1c.3: enabled 0 |
| [SPEW ] PCI: 00:1c.4: enabled 0 |
| [SPEW ] PCI: 00:1c.5: enabled 0 |
| [SPEW ] PCI: 00:1c.6: enabled 0 |
| [SPEW ] PCI: 00:1c.7: enabled 0 |
| [SPEW ] PCI: 00:1d.0: enabled 1 |
| [SPEW ] PCI: 00:1e.0: enabled 0 |
| [SPEW ] PCI: 00:1f.0: enabled 1 |
| [SPEW ] PCI: 00:1f.2: enabled 1 |
| [SPEW ] PCI: 00:1f.3: enabled 1 |
| [SPEW ] PCI: 00:1f.5: enabled 0 |
| [SPEW ] PCI: 00:1f.6: enabled 1 |
| [SPEW ] PCI: 01:00.0: enabled 1 |
| [SPEW ] PNP: 00ff.1: enabled 1 |
| [SPEW ] PNP: 0c31.0: enabled 1 |
| [SPEW ] PNP: 00ff.2: enabled 1 |
| [SPEW ] I2C: 01:54: enabled 1 |
| [SPEW ] I2C: 01:55: enabled 1 |
| [SPEW ] I2C: 01:56: enabled 1 |
| [SPEW ] I2C: 01:57: enabled 1 |
| [SPEW ] I2C: 01:5c: enabled 1 |
| [SPEW ] I2C: 01:5d: enabled 1 |
| [SPEW ] I2C: 01:5e: enabled 1 |
| [SPEW ] I2C: 01:5f: enabled 1 |
| [SPEW ] PCI: 02:00.0: enabled 1 |
| [SPEW ] NONE: enabled 1 |
| [SPEW ] APIC: 00: enabled 1 |
| [SPEW ] APIC: 01: enabled 1 |
| [SPEW ] APIC: 03: enabled 1 |
| [SPEW ] APIC: 02: enabled 1 |
| [DEBUG] BS: BS_DEV_INIT run times (exec / console): 57 / 1 ms |
| [INFO ] Found TPM ST33ZP24 by ST Microelectronics |
| [INFO ] TPM: Handle S3 resume. |
| [DEBUG] TPM: Resume |
| [DEBUG] TPM: command 0x99 returned 0x0 |
| [INFO ] TPM: setup succeeded |
| [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 89 / 0 ms |
| [INFO ] Finalize devices... |
| [DEBUG] PCI: 00:1f.0 final |
| [DEBUG] apm_control: Finalizing SMM. |
| [DEBUG] APMC done. |
| [INFO ] Devices finalized |
| [DEBUG] Trying to find the wakeup vector... |
| [DEBUG] Looking on 0x000f6630 for valid checksum |
| [DEBUG] Checksum 1 passed |
| [DEBUG] Checksum 2 passed all OK |
| [DEBUG] RSDP found at 0x000f6630 |
| [DEBUG] RSDT found at 0x7ff37030 ends at 0x7ff37070 |
| [DEBUG] FADT found at 0x7ff3ab30 |
| [DEBUG] FACS found at 0x7ff37240 |
| [DEBUG] OS waking vector is 0x0009a1f0 |