| |
| coreboot-4.12-284-g165efa1b86 Tue May 26 15:09:50 UTC 2020 bootblock starting (log level: 6)... |
| FMAP: Found "FLASH" version 1.1 at 0x710000. |
| FMAP: base = 0xff800000 size = 0x800000 #areas = 4 |
| FMAP: area COREBOOT found @ 710200 (982528 bytes) |
| CBFS: Locating 'fallback/romstage' |
| CBFS: Found @ offset 80 size 1067c |
| BS: bootblock times (exec / console): total (unknown) / 1 ms |
| |
| |
| coreboot-4.12-284-g165efa1b86 Tue May 26 15:09:50 UTC 2020 romstage starting (log level: 6)... |
| Setting up static southbridge registers... done. |
| Disabling Watchdog reboot... done. |
| Setting up static northbridge registers... done. |
| SMBus controller enabled |
| Setting up Chipset Initialization Registers (CIR) |
| SB: Resume from S3 detected. |
| Intel ME early init |
| Intel ME firmware is ready |
| ME: Requested 32MB UMA |
| FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) |
| SMM Memory Map |
| SMRAM : 0xbf800000 0x800000 |
| Subregion 0: 0xbf800000 0x700000 |
| Subregion 1: 0xbff00000 0x100000 |
| Subregion 2: 0xc0000000 0x0 |
| MTRR Range: Start=bf000000 End=bf800000 (Size 800000) |
| MTRR Range: Start=bf800000 End=c0000000 (Size 800000) |
| MTRR Range: Start=ff800000 End=0 (Size 800000) |
| BS: romstage times (exec / console): total (unknown) / 1 ms |
| |
| |
| coreboot-4.12-284-g165efa1b86 Tue May 26 15:09:50 UTC 2020 postcar starting (log level: 6)... |
| Jumping to image. |
| |
| |
| coreboot-4.12-284-g165efa1b86 Tue May 26 15:09:50 UTC 2020 ramstage starting (log level: 6)... |
| S3 Resume |
| Disabling PEG10. |
| Enumerating buses... |
| Root Device scanning... |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| DOMAIN: 0000 scanning... |
| PCI: pci_scan_bus for bus 00 |
| PCI: 00:00.0 [8086/0044] enabled |
| PCI: 00:02.0 [8086/0046] enabled |
| PCI: 00:16.0 [8086/3b64] enabled |
| PCI: 00:16.1: Disabling device |
| PCI: 00:16.2: Disabling device |
| PCI: 00:16.3: Disabling device |
| PCI: 00:19.0 [8086/10ea] enabled |
| PCI: 00:1a.0 [8086/3b3c] enabled |
| PCI: 00:1b.0 [8086/3b56] enabled |
| PCI: 00:1c.0 subordinate bus PCI Express |
| PCI: 00:1c.0 [8086/3b42] enabled |
| PCI: 00:1c.1 subordinate bus PCI Express |
| PCI: 00:1c.1 [8086/3b44] enabled |
| PCI: 00:1c.2: Disabling device |
| PCI: 00:1c.2 [8086/3b46] disabled No operations |
| PCI: 00:1c.3 subordinate bus PCI Express |
| PCI: 00:1c.3 [8086/3b48] enabled |
| PCI: 00:1c.4 subordinate bus PCI Express |
| PCI: 00:1c.4 [8086/3b4a] enabled |
| PCI: 00:1c.5: Disabling device |
| PCI: 00:1c.5 [8086/3b4c] disabled No operations |
| PCI: 00:1c.6: Disabling device |
| PCI: 00:1c.6 [8086/3b4e] disabled No operations |
| PCI: 00:1c.7: Disabling device |
| PCI: 00:1c.7 [8086/3b50] disabled No operations |
| PCI: 00:1d.0 [8086/3b34] enabled |
| PCI: 00:1e.0 [8086/2448] enabled |
| PCI: 00:1f.0 [8086/3b07] enabled |
| PCI: 00:1f.2 [8086/3b2e] enabled |
| PCI: 00:1f.3 [8086/3b30] enabled |
| PCI: 00:1f.4: Disabling device |
| PCI: 00:1f.5: Disabling device |
| PCI: 00:1f.5 [8086/3b2d] disabled No operations |
| PCI: 00:1f.6 [8086/3b32] enabled |
| PCI: Leftover static devices: |
| PCI: 00:01.0 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:1f.4 |
| PCI: Check your devicetree.cb. |
| PCI: 00:1c.0 scanning... |
| PCI: pci_scan_bus for bus 01 |
| scan_bus: bus PCI: 00:1c.0 finished in 0 msecs |
| PCI: 00:1c.1 scanning... |
| PCI: pci_scan_bus for bus 02 |
| scan_bus: bus PCI: 00:1c.1 finished in 0 msecs |
| PCI: 00:1c.3 scanning... |
| PCI: pci_scan_bus for bus 03 |
| scan_bus: bus PCI: 00:1c.3 finished in 0 msecs |
| PCI: 00:1c.4 scanning... |
| PCI: pci_scan_bus for bus 04 |
| PCI: 04:00.0 [168c/002a] enabled |
| Enabling Common Clock Configuration |
| ASPM: Enabled L1 |
| PCIe: Max_Payload_Size adjusted to 128 |
| Failed to enable LTR for dev = PCI: 04:00.0 |
| scan_bus: bus PCI: 00:1c.4 finished in 0 msecs |
| PCI: 00:1e.0 scanning... |
| PCI: pci_scan_bus for bus 05 |
| scan_bus: bus PCI: 00:1e.0 finished in 0 msecs |
| PCI: 00:1f.0 scanning... |
| PNP: 164e.3 enabled |
| PNP: 164e.2 disabled |
| PNP: 164e.7 disabled |
| PNP: 164e.19 disabled |
| PNP: 0c31.0 enabled |
| PMH7: ID 04 Revision 01 |
| PNP: 00ff.1 enabled |
| H8: EC Firmware ID 6QHT34WW-3.18, Version 5.01B |
| H8: BDC not installed |
| H8: WWAN detection not implemented. Assuming WWAN installed |
| dock is connected |
| PNP: 00ff.2 enabled |
| scan_bus: bus PCI: 00:1f.0 finished in 7 msecs |
| PCI: 00:1f.3 scanning... |
| bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled |
| scan_bus: bus PCI: 00:1f.3 finished in 0 msecs |
| scan_bus: bus DOMAIN: 0000 finished in 7 msecs |
| scan_bus: bus Root Device finished in 7 msecs |
| done |
| BS: BS_DEV_ENUMERATE run times (exec / console): 8 / 0 ms |
| FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) |
| MRC: Checking cached data update for 'RW_MRC_CACHE'. |
| Manufacturer: c2 |
| SF: Detected c2 2017 with sector size 0x1000, total 0x800000 |
| found VGA at PCI: 00:02.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| Adding PCIe enhanced config space BAR 0xe0000000-0xf0000000. |
| ram_before_4g_top: 0xbf800000 |
| TOUUD: 0x2380 |
| PNP: 00ff.1 missing read_resources |
| PNP: 00ff.2 missing read_resources |
| Done reading resources. |
| skipping PNP: 164e.3@29 fixed resource, size=0! |
| skipping PNP: 164e.3@f0 fixed resource, size=0! |
| skipping PNP: 00ff.2@60 fixed resource, size=0! |
| skipping PNP: 00ff.2@62 fixed resource, size=0! |
| skipping PNP: 00ff.2@64 fixed resource, size=0! |
| skipping PNP: 00ff.2@66 fixed resource, size=0! |
| Setting resources... |
| PCI: 00:02.0 10 <- [0x00cf800000 - 0x00cfbfffff] size 0x00400000 gran 0x16 mem64 |
| PCI: 00:02.0 20 <- [0x0000001840 - 0x0000001847] size 0x00000008 gran 0x03 io |
| PCI: 00:16.0 10 <- [0x00cfd2a000 - 0x00cfd2a00f] size 0x00000010 gran 0x04 mem64 |
| PCI: 00:19.0 10 <- [0x00cfd00000 - 0x00cfd1ffff] size 0x00020000 gran 0x11 mem |
| PCI: 00:19.0 14 <- [0x00cfd24000 - 0x00cfd24fff] size 0x00001000 gran 0x0c mem |
| PCI: 00:19.0 18 <- [0x0000001800 - 0x000000181f] size 0x00000020 gran 0x05 io |
| PCI: 00:1a.0 10 <- [0x00cfd27000 - 0x00cfd273ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1b.0 10 <- [0x00cfd20000 - 0x00cfd23fff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| PCI: 00:1c.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| PCI: 00:1c.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 01 mem |
| PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| PCI: 00:1c.1 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.1 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 02 mem |
| PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io |
| PCI: 00:1c.3 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.3 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 03 mem |
| PCI: 00:1c.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io |
| PCI: 00:1c.4 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 04 prefmem |
| PCI: 00:1c.4 20 <- [0x00cfc00000 - 0x00cfcfffff] size 0x00100000 gran 0x14 bus 04 mem |
| PCI: 04:00.0 10 <- [0x00cfc00000 - 0x00cfc0ffff] size 0x00010000 gran 0x10 mem64 |
| PCI: 00:1d.0 10 <- [0x00cfd28000 - 0x00cfd283ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io |
| PCI: 00:1e.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 05 prefmem |
| PCI: 00:1e.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 05 mem |
| PNP: 164e.3 60 <- [0x0000000200 - 0x0000000207] size 0x00000008 gran 0x03 io |
| PNP: 164e.3 29 <- [0x00000000b0 - 0x00000000af] size 0x00000000 gran 0x00 irq |
| PNP: 164e.3 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq |
| PNP: 164e.3 f0 <- [0x0000000082 - 0x0000000081] size 0x00000000 gran 0x00 irq |
| PNP: 00ff.1 missing set_resources |
| PNP: 00ff.2 missing set_resources |
| PCI: 00:1f.2 10 <- [0x0000001848 - 0x000000184f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x0000001858 - 0x000000185b] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x0000001850 - 0x0000001857] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x000000185c - 0x000000185f] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000001820 - 0x000000183f] size 0x00000020 gran 0x05 io |
| PCI: 00:1f.2 24 <- [0x00cfd26000 - 0x00cfd267ff] size 0x00000800 gran 0x0b mem |
| PCI: 00:1f.3 10 <- [0x00cfd29000 - 0x00cfd290ff] size 0x00000100 gran 0x08 mem64 |
| PCI: 00:1f.6 10 <- [0x00cfd25000 - 0x00cfd25fff] size 0x00001000 gran 0x0c mem64 |
| Done setting resources. |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES run times (exec / console): 1 / 0 ms |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 17aa/2193 |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:02.0 subsystem <- 17aa/215a |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:16.0 subsystem <- 8086/3b64 |
| PCI: 00:16.0 cmd <- 02 |
| PCI: 00:19.0 subsystem <- 17aa/2153 |
| PCI: 00:19.0 cmd <- 103 |
| PCI: 00:1a.0 subsystem <- 17aa/2163 |
| PCI: 00:1a.0 cmd <- 102 |
| PCI: 00:1b.0 subsystem <- 17aa/215e |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0013 |
| PCI: 00:1c.0 cmd <- 100 |
| PCI: 00:1c.1 bridge ctrl <- 0013 |
| PCI: 00:1c.1 cmd <- 100 |
| PCI: 00:1c.3 bridge ctrl <- 0013 |
| PCI: 00:1c.3 cmd <- 100 |
| PCI: 00:1c.4 bridge ctrl <- 0013 |
| PCI: 00:1c.4 cmd <- 106 |
| PCI: 00:1d.0 subsystem <- 17aa/2163 |
| PCI: 00:1d.0 cmd <- 102 |
| PCI: 00:1e.0 bridge ctrl <- 0013 |
| PCI: 00:1e.0 subsystem <- 8086/2448 |
| PCI: 00:1e.0 cmd <- 100 |
| PCI: 00:1f.0 subsystem <- 17aa/2166 |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 17aa/2168 |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 00:1f.3 subsystem <- 17aa/2167 |
| PCI: 00:1f.3 cmd <- 103 |
| PCI: 00:1f.6 subsystem <- 8086/3b32 |
| PCI: 00:1f.6 cmd <- 02 |
| PCI: 04:00.0 cmd <- 02 |
| done. |
| Found TPM ST33ZP24 by ST Microelectronics |
| TPM: Handle S3 resume. |
| TPM: Resume |
| TPM: command 0x99 returned 0x9 |
| TPM: Resume failed (0x9). |
| BS: BS_DEV_INIT entry times (exec / console): 4 / 0 ms |
| Initializing devices... |
| CPU_CLUSTER: 0 init |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x00000000bf800000 size 0xbf740000 type 6 |
| 0x00000000bf800000 - 0x00000000d0000000 size 0x10800000 type 0 |
| 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 |
| 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 |
| 0x0000000100000000 - 0x0000000238000000 size 0x138000000 type 6 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 4/6. |
| MTRR: WB selected as default type. |
| MTRR: 0 base 0x00000000bf800000 mask 0x0000000fff800000 type 0 |
| MTRR: 1 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 |
| MTRR: 2 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 |
| MTRR: 3 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| CPU has 2 cores, 4 threads enabled. |
| Setting up SMI for CPU |
| Will perform SMM setup. |
| FMAP: area COREBOOT found @ 710200 (982528 bytes) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 10780 size 3400 |
| microcode: sig=0x20652 pf=0x10 revision=0x11 |
| CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz. |
| Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 |
| Processing 16 relocs. Offset value of 0x00030000 |
| Attempting to start 3 APs |
| Waiting for 10ms after sending INIT. |
| Waiting for 1st SIPI to complete...done. |
| Waiting for 2nd SIPI to complete...AP: slot 1 apic_id 1. |
| done. |
| AP: slot 2 apic_id 5. |
| AP: slot 3 apic_id 4. |
| Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b0 memsize: 0x1b0 |
| Processing 13 relocs. Offset value of 0x00038000 |
| SMM Module: stub loaded at 0x00038000. Will call 0xbf7a8c97(0x00000000) |
| Installing SMM handler to 0xbf800000 |
| Loading module at 0xbf810000 with entry 0xbf81029a. filesize: 0x1590 memsize: 0x55b8 |
| Processing 66 relocs. Offset value of 0xbf810000 |
| Loading module at 0xbf808000 with entry 0xbf808000. filesize: 0x1b0 memsize: 0x1b0 |
| Processing 13 relocs. Offset value of 0xbf808000 |
| SMM Module: placing jmp sequence at 0xbf807c00 rel16 0x03fd |
| SMM Module: placing jmp sequence at 0xbf807800 rel16 0x07fd |
| SMM Module: placing jmp sequence at 0xbf807400 rel16 0x0bfd |
| SMM Module: stub loaded at 0xbf808000. Will call 0xbf81029a(0x00000000) |
| Initializing Southbridge SMI... |
| |
| New SMBASE 0xbf800000 |
| In relocation handler: cpu 0 |
| New SMBASE=0xbf800000 |
| Writing SMRR. base = 0xbf800006, mask=0xff800800 |
| Relocation complete. |
| New SMBASE 0xbf7ffc00 |
| microcode: Update skipped, already up-to-date |
| In relocation handler: cpu 1 |
| New SMBASE=0xbf7ffc00 |
| Writing SMRR. base = 0xbf800006, mask=0xff800800 |
| Relocation complete. |
| New SMBASE 0xbf7ff400 |
| In relocation handler: cpu 3 |
| New SMBASE=0xbf7ff400 |
| Writing SMRR. base = 0xbf800006, mask=0xff800800 |
| microcode: Update skipped, already up-to-date |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| New SMBASE 0xbf7ff800 |
| In relocation handler: cpu 2 |
| New SMBASE=0xbf7ff800 |
| Writing SMRR. base = 0xbf800006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| Initializing CPU #0 |
| CPU: vendor Intel device 20652 |
| CPU: family 06, model 25, stepping 02 |
| Enabling cache |
| CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz. |
| CPU:lapic=0, boot_cpu=1 |
| Setting up local APIC... |
| apic_id: 0x00 done. |
| VMX status: enabled |
| IA32_FEATURE_CONTROL status: locked |
| model_x06ax: frequency set to 2527 |
| Turbo is available and visible |
| CPU #0 initialized |
| Initializing CPU #1 |
| Initializing CPU #3 |
| CPU: vendor Intel device 20652 |
| CPU: family 06, model 25, stepping 02 |
| Initializing CPU #2 |
| Enabling cache |
| CPU: vendor Intel device 20652 |
| CPU: vendor Intel device 20652 |
| CPU: family 06, model 25, stepping 02 |
| CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz. |
| CPU: family 06, model 25, stepping 02 |
| CPU:lapic=1, boot_cpu=0 |
| Enabling cache |
| Setting up local APIC... |
| Enabling cache |
| apic_id: 0x01 done. |
| VMX status: enabled |
| CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz. |
| IA32_FEATURE_CONTROL status: locked |
| CPU:lapic=4, boot_cpu=0 |
| CPU: Intel(R) Core(TM) i5 CPU M 540 @ 2.53GHz. |
| Setting up local APIC... |
| model_x06ax: frequency set to 2527 |
| apic_id: 0x04 done. |
| CPU #1 initialized |
| VMX status: enabled |
| CPU:lapic=5, boot_cpu=0 |
| IA32_FEATURE_CONTROL status: locked |
| Setting up local APIC... |
| apic_id: 0x05 done. |
| model_x06ax: frequency set to 2527 |
| VMX status: enabled |
| CPU #3 initialized |
| IA32_FEATURE_CONTROL status: locked |
| model_x06ax: frequency set to 2527 |
| CPU #2 initialized |
| bsp_do_flight_plan done after 6 msecs. |
| Initializing southbridge SMI... |
| SMI_STS: |
| GPE0_STS: GPIO14 GPIO11 GPIO9 GPIO2 GPIO0 |
| ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 |
| TCO_STS: |
| Locking SMM. |
| CPU_CLUSTER: 0 init finished in 16 msecs |
| PCI: 00:00.0 init |
| PCI: 00:00.0 init finished in 0 msecs |
| PCI: 00:02.0 init |
| GT Power Management Init (post VBIOS) |
| PCI: 00:02.0 init finished in 0 msecs |
| PCI: 00:16.0 init |
| ME: BIOS path: S3 Wake |
| PCI: 00:16.0: Disabling device |
| PCI: 00:16.0 init finished in 0 msecs |
| PCI: 00:19.0 init |
| PCI: 00:19.0 init finished in 0 msecs |
| PCI: 00:1a.0 init |
| EHCI: Setting up controller.. done. |
| PCI: 00:1a.0 init finished in 0 msecs |
| PCI: 00:1b.0 init |
| Azalia: base = cfd20000 |
| Azalia: V1CTL disabled. |
| Azalia: codec_mask = 09 |
| Azalia: Initializing codec #3 |
| Azalia: codec viddid: 80862804 |
| Azalia: verb_size: 16 |
| Azalia: verb loaded. |
| Azalia: Initializing codec #0 |
| Azalia: codec viddid: 14f15069 |
| Azalia: verb_size: 44 |
| Azalia: verb loaded. |
| PCI: 00:1b.0 init finished in 4 msecs |
| PCI: 00:1d.0 init |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 0 msecs |
| PCI: 00:1e.0 init |
| PCI init. |
| PCI: 00:1e.0 init finished in 0 msecs |
| PCI: 00:1f.0 init |
| pch: lpc_init |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x01 |
| Set power off after power failure. |
| NMI sources disabled. |
| Mobile 5 PM init |
| rtc_failed = 0x0 |
| PCI: 00:1f.0 init finished in 0 msecs |
| PCI: 00:1f.2 init |
| SATA: Initializing... |
| SATA: Controller in AHCI mode. |
| ABAR: 0xcfd26000 |
| PCI: 00:1f.2 init finished in 0 msecs |
| PCI: 00:1f.3 init |
| PCI: 00:1f.3 init finished in 0 msecs |
| PCI: 00:1f.6 init |
| Thermal init start. |
| Thermal init done. |
| PCI: 00:1f.6 init finished in 0 msecs |
| PCI: 04:00.0 init |
| PCI: 04:00.0 init finished in 0 msecs |
| PNP: 164e.3 init |
| PNP: 164e.3 init finished in 0 msecs |
| PNP: 00ff.2 init |
| PNP: 00ff.2 init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 init |
| I2C: 01:54 init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 init |
| I2C: 01:55 init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 init |
| I2C: 01:56 init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 init |
| I2C: 01:57 init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c init |
| Locking EEPROM RFID |
| init EEPROM done |
| I2C: 01:5c init finished in 26 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d init |
| I2C: 01:5d init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e init |
| I2C: 01:5e init finished in 0 msecs |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f init |
| I2C: 01:5f init finished in 0 msecs |
| Devices initialized |
| BS: BS_DEV_INIT run times (exec / console): 49 / 0 ms |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| Trying to find the wakeup vector... |
| Looking on 0x000f6750 for valid checksum |
| Checksum 1 passed |
| Checksum 2 passed all OK |
| RSDP found at 0x000f6750 |
| RSDT found at 0xbf74f030 ends at 0xbf74f06c |
| FADT found at 0xbf752d80 |
| FACS found at 0xbf74f240 |
| OS waking vector is 0x0009a1d0 |
| Restore GNVS pointer to 0xbf74e000 |
| |