Gerd Hoffmann | e144bb7 | 2013-06-03 16:30:18 +0200 | [diff] [blame^] | 1 | #include "config.h" // CONFIG_* |
| 2 | #include "output.h" // dprintf |
| 3 | #include "string.h" // memcpy_fl |
| 4 | #include "util.h" // timer_calc |
| 5 | #include "x86.h" // readl |
| 6 | #include "malloc.h" // memalign_low |
| 7 | #include "pci.h" // pci_bdf_to_bus |
| 8 | #include "pci_regs.h" // PCI_BASE_ADDRESS_0 |
| 9 | #include "usb.h" // struct usb_s |
| 10 | #include "usb-xhci.h" // struct ehci_qh |
| 11 | #include "biosvar.h" // GET_LOWFLAT |
| 12 | |
| 13 | // -------------------------------------------------------------- |
| 14 | // configuration |
| 15 | |
| 16 | #define XHCI_RING_ITEMS 16 |
| 17 | #define XHCI_RING_SIZE (XHCI_RING_ITEMS*sizeof(struct xhci_trb)) |
| 18 | |
| 19 | /* |
| 20 | * xhci_ring structs are allocated with XHCI_RING_SIZE alignment, |
| 21 | * then we can get it from a trb pointer (provided by evt ring). |
| 22 | */ |
| 23 | #define XHCI_RING(_trb) \ |
| 24 | ((struct xhci_ring*)((u32)(_trb) & ~(XHCI_RING_SIZE-1))) |
| 25 | |
| 26 | // -------------------------------------------------------------- |
| 27 | // bit definitions |
| 28 | |
| 29 | #define XHCI_CMD_RS (1<<0) |
| 30 | #define XHCI_CMD_HCRST (1<<1) |
| 31 | #define XHCI_CMD_INTE (1<<2) |
| 32 | #define XHCI_CMD_HSEE (1<<3) |
| 33 | #define XHCI_CMD_LHCRST (1<<7) |
| 34 | #define XHCI_CMD_CSS (1<<8) |
| 35 | #define XHCI_CMD_CRS (1<<9) |
| 36 | #define XHCI_CMD_EWE (1<<10) |
| 37 | #define XHCI_CMD_EU3S (1<<11) |
| 38 | |
| 39 | #define XHCI_STS_HCH (1<<0) |
| 40 | #define XHCI_STS_HSE (1<<2) |
| 41 | #define XHCI_STS_EINT (1<<3) |
| 42 | #define XHCI_STS_PCD (1<<4) |
| 43 | #define XHCI_STS_SSS (1<<8) |
| 44 | #define XHCI_STS_RSS (1<<9) |
| 45 | #define XHCI_STS_SRE (1<<10) |
| 46 | #define XHCI_STS_CNR (1<<11) |
| 47 | #define XHCI_STS_HCE (1<<12) |
| 48 | |
| 49 | #define XHCI_PORTSC_CCS (1<<0) |
| 50 | #define XHCI_PORTSC_PED (1<<1) |
| 51 | #define XHCI_PORTSC_OCA (1<<3) |
| 52 | #define XHCI_PORTSC_PR (1<<4) |
| 53 | #define XHCI_PORTSC_PLS_SHIFT 5 |
| 54 | #define XHCI_PORTSC_PLS_MASK 0xf |
| 55 | #define XHCI_PORTSC_PP (1<<9) |
| 56 | #define XHCI_PORTSC_SPEED_SHIFT 10 |
| 57 | #define XHCI_PORTSC_SPEED_MASK 0xf |
| 58 | #define XHCI_PORTSC_SPEED_FULL (1<<10) |
| 59 | #define XHCI_PORTSC_SPEED_LOW (2<<10) |
| 60 | #define XHCI_PORTSC_SPEED_HIGH (3<<10) |
| 61 | #define XHCI_PORTSC_SPEED_SUPER (4<<10) |
| 62 | #define XHCI_PORTSC_PIC_SHIFT 14 |
| 63 | #define XHCI_PORTSC_PIC_MASK 0x3 |
| 64 | #define XHCI_PORTSC_LWS (1<<16) |
| 65 | #define XHCI_PORTSC_CSC (1<<17) |
| 66 | #define XHCI_PORTSC_PEC (1<<18) |
| 67 | #define XHCI_PORTSC_WRC (1<<19) |
| 68 | #define XHCI_PORTSC_OCC (1<<20) |
| 69 | #define XHCI_PORTSC_PRC (1<<21) |
| 70 | #define XHCI_PORTSC_PLC (1<<22) |
| 71 | #define XHCI_PORTSC_CEC (1<<23) |
| 72 | #define XHCI_PORTSC_CAS (1<<24) |
| 73 | #define XHCI_PORTSC_WCE (1<<25) |
| 74 | #define XHCI_PORTSC_WDE (1<<26) |
| 75 | #define XHCI_PORTSC_WOE (1<<27) |
| 76 | #define XHCI_PORTSC_DR (1<<30) |
| 77 | #define XHCI_PORTSC_WPR (1<<31) |
| 78 | |
| 79 | #define TRB_C (1<<0) |
| 80 | #define TRB_TYPE_SHIFT 10 |
| 81 | #define TRB_TYPE_MASK 0x3f |
| 82 | #define TRB_TYPE(t) (((t) >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) |
| 83 | |
| 84 | #define TRB_EV_ED (1<<2) |
| 85 | |
| 86 | #define TRB_TR_ENT (1<<1) |
| 87 | #define TRB_TR_ISP (1<<2) |
| 88 | #define TRB_TR_NS (1<<3) |
| 89 | #define TRB_TR_CH (1<<4) |
| 90 | #define TRB_TR_IOC (1<<5) |
| 91 | #define TRB_TR_IDT (1<<6) |
| 92 | #define TRB_TR_TBC_SHIFT 7 |
| 93 | #define TRB_TR_TBC_MASK 0x3 |
| 94 | #define TRB_TR_BEI (1<<9) |
| 95 | #define TRB_TR_TLBPC_SHIFT 16 |
| 96 | #define TRB_TR_TLBPC_MASK 0xf |
| 97 | #define TRB_TR_FRAMEID_SHIFT 20 |
| 98 | #define TRB_TR_FRAMEID_MASK 0x7ff |
| 99 | #define TRB_TR_SIA (1<<31) |
| 100 | |
| 101 | #define TRB_TR_DIR (1<<16) |
| 102 | |
| 103 | #define TRB_CR_SLOTID_SHIFT 24 |
| 104 | #define TRB_CR_SLOTID_MASK 0xff |
| 105 | #define TRB_CR_EPID_SHIFT 16 |
| 106 | #define TRB_CR_EPID_MASK 0x1f |
| 107 | |
| 108 | #define TRB_CR_BSR (1<<9) |
| 109 | #define TRB_CR_DC (1<<9) |
| 110 | |
| 111 | #define TRB_LK_TC (1<<1) |
| 112 | |
| 113 | #define TRB_INTR_SHIFT 22 |
| 114 | #define TRB_INTR_MASK 0x3ff |
| 115 | #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) |
| 116 | |
| 117 | typedef enum TRBType { |
| 118 | TRB_RESERVED = 0, |
| 119 | TR_NORMAL, |
| 120 | TR_SETUP, |
| 121 | TR_DATA, |
| 122 | TR_STATUS, |
| 123 | TR_ISOCH, |
| 124 | TR_LINK, |
| 125 | TR_EVDATA, |
| 126 | TR_NOOP, |
| 127 | CR_ENABLE_SLOT, |
| 128 | CR_DISABLE_SLOT, |
| 129 | CR_ADDRESS_DEVICE, |
| 130 | CR_CONFIGURE_ENDPOINT, |
| 131 | CR_EVALUATE_CONTEXT, |
| 132 | CR_RESET_ENDPOINT, |
| 133 | CR_STOP_ENDPOINT, |
| 134 | CR_SET_TR_DEQUEUE, |
| 135 | CR_RESET_DEVICE, |
| 136 | CR_FORCE_EVENT, |
| 137 | CR_NEGOTIATE_BW, |
| 138 | CR_SET_LATENCY_TOLERANCE, |
| 139 | CR_GET_PORT_BANDWIDTH, |
| 140 | CR_FORCE_HEADER, |
| 141 | CR_NOOP, |
| 142 | ER_TRANSFER = 32, |
| 143 | ER_COMMAND_COMPLETE, |
| 144 | ER_PORT_STATUS_CHANGE, |
| 145 | ER_BANDWIDTH_REQUEST, |
| 146 | ER_DOORBELL, |
| 147 | ER_HOST_CONTROLLER, |
| 148 | ER_DEVICE_NOTIFICATION, |
| 149 | ER_MFINDEX_WRAP, |
| 150 | } TRBType; |
| 151 | |
| 152 | typedef enum TRBCCode { |
| 153 | CC_INVALID = 0, |
| 154 | CC_SUCCESS, |
| 155 | CC_DATA_BUFFER_ERROR, |
| 156 | CC_BABBLE_DETECTED, |
| 157 | CC_USB_TRANSACTION_ERROR, |
| 158 | CC_TRB_ERROR, |
| 159 | CC_STALL_ERROR, |
| 160 | CC_RESOURCE_ERROR, |
| 161 | CC_BANDWIDTH_ERROR, |
| 162 | CC_NO_SLOTS_ERROR, |
| 163 | CC_INVALID_STREAM_TYPE_ERROR, |
| 164 | CC_SLOT_NOT_ENABLED_ERROR, |
| 165 | CC_EP_NOT_ENABLED_ERROR, |
| 166 | CC_SHORT_PACKET, |
| 167 | CC_RING_UNDERRUN, |
| 168 | CC_RING_OVERRUN, |
| 169 | CC_VF_ER_FULL, |
| 170 | CC_PARAMETER_ERROR, |
| 171 | CC_BANDWIDTH_OVERRUN, |
| 172 | CC_CONTEXT_STATE_ERROR, |
| 173 | CC_NO_PING_RESPONSE_ERROR, |
| 174 | CC_EVENT_RING_FULL_ERROR, |
| 175 | CC_INCOMPATIBLE_DEVICE_ERROR, |
| 176 | CC_MISSED_SERVICE_ERROR, |
| 177 | CC_COMMAND_RING_STOPPED, |
| 178 | CC_COMMAND_ABORTED, |
| 179 | CC_STOPPED, |
| 180 | CC_STOPPED_LENGTH_INVALID, |
| 181 | CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, |
| 182 | CC_ISOCH_BUFFER_OVERRUN = 31, |
| 183 | CC_EVENT_LOST_ERROR, |
| 184 | CC_UNDEFINED_ERROR, |
| 185 | CC_INVALID_STREAM_ID_ERROR, |
| 186 | CC_SECONDARY_BANDWIDTH_ERROR, |
| 187 | CC_SPLIT_TRANSACTION_ERROR |
| 188 | } TRBCCode; |
| 189 | |
| 190 | enum { |
| 191 | PLS_U0 = 0, |
| 192 | PLS_U1 = 1, |
| 193 | PLS_U2 = 2, |
| 194 | PLS_U3 = 3, |
| 195 | PLS_DISABLED = 4, |
| 196 | PLS_RX_DETECT = 5, |
| 197 | PLS_INACTIVE = 6, |
| 198 | PLS_POLLING = 7, |
| 199 | PLS_RECOVERY = 8, |
| 200 | PLS_HOT_RESET = 9, |
| 201 | PLS_COMPILANCE_MODE = 10, |
| 202 | PLS_TEST_MODE = 11, |
| 203 | PLS_RESUME = 15, |
| 204 | }; |
| 205 | |
| 206 | #define xhci_get_field(data, field) \ |
| 207 | (((data) >> field##_SHIFT) & field##_MASK) |
| 208 | |
| 209 | // -------------------------------------------------------------- |
| 210 | // state structs |
| 211 | |
| 212 | struct xhci_ring { |
| 213 | struct xhci_trb ring[XHCI_RING_ITEMS]; |
| 214 | struct xhci_trb evt; |
| 215 | u32 eidx; |
| 216 | u32 nidx; |
| 217 | u32 cs; |
| 218 | struct mutex_s lock; |
| 219 | }; |
| 220 | |
| 221 | struct usb_xhci_s { |
| 222 | struct usb_s usb; |
| 223 | struct usbhub_s hub; |
| 224 | |
| 225 | /* devinfo */ |
| 226 | u32 baseaddr; |
| 227 | u32 xcap; |
| 228 | u32 ports; |
| 229 | u32 slots; |
| 230 | |
| 231 | /* xhci registers */ |
| 232 | struct xhci_caps *caps; |
| 233 | struct xhci_op *op; |
| 234 | struct xhci_pr *pr; |
| 235 | struct xhci_ir *ir; |
| 236 | struct xhci_db *db; |
| 237 | |
| 238 | /* xhci data structures */ |
| 239 | struct xhci_devlist *devs; |
| 240 | struct xhci_ring *cmds; |
| 241 | struct xhci_ring *evts; |
| 242 | struct xhci_er_seg *eseg; |
| 243 | |
| 244 | /* usb devices */ |
| 245 | struct hlist_head list; |
| 246 | }; |
| 247 | |
| 248 | struct xhci_device { |
| 249 | struct xhci_devctx devctx; |
| 250 | struct xhci_inctx inctx; |
| 251 | |
| 252 | struct usbdevice_s *usbdev; |
| 253 | struct usb_xhci_s *xhci; |
| 254 | u32 slotid; |
| 255 | struct hlist_node next; |
| 256 | }; |
| 257 | |
| 258 | struct xhci_pipe { |
| 259 | struct xhci_ring reqs; |
| 260 | |
| 261 | struct usb_pipe pipe; |
| 262 | struct xhci_device *dev; |
| 263 | u32 epid; |
| 264 | void *buf; |
| 265 | int bufused; |
| 266 | }; |
| 267 | |
| 268 | // -------------------------------------------------------------- |
| 269 | // tables |
| 270 | |
| 271 | static const char *speed_name[16] = { |
| 272 | [ 0 ] = " - ", |
| 273 | [ 1 ] = "Full", |
| 274 | [ 2 ] = "Low", |
| 275 | [ 3 ] = "High", |
| 276 | [ 4 ] = "Super", |
| 277 | }; |
| 278 | |
| 279 | static const int speed_from_xhci[16] = { |
| 280 | [ 0 ... 15 ] = -1, |
| 281 | [ 1 ] = USB_FULLSPEED, |
| 282 | [ 2 ] = USB_LOWSPEED, |
| 283 | [ 3 ] = USB_HIGHSPEED, |
| 284 | [ 4 ] = USB_SUPERSPEED, |
| 285 | }; |
| 286 | |
| 287 | static const int speed_to_xhci[] = { |
| 288 | [ USB_FULLSPEED ] = 1, |
| 289 | [ USB_LOWSPEED ] = 2, |
| 290 | [ USB_HIGHSPEED ] = 3, |
| 291 | [ USB_SUPERSPEED ] = 4, |
| 292 | }; |
| 293 | |
| 294 | static const int speed_to_ctlsize[] = { |
| 295 | [ USB_FULLSPEED ] = 8, |
| 296 | [ USB_LOWSPEED ] = 8, |
| 297 | [ USB_HIGHSPEED ] = 64, |
| 298 | [ USB_SUPERSPEED ] = 256, |
| 299 | }; |
| 300 | |
| 301 | static const int eptype_to_xhci_in[] = { |
| 302 | [ USB_ENDPOINT_XFER_CONTROL] = 4, |
| 303 | [ USB_ENDPOINT_XFER_ISOC ] = 5, |
| 304 | [ USB_ENDPOINT_XFER_BULK ] = 6, |
| 305 | [ USB_ENDPOINT_XFER_INT ] = 7, |
| 306 | }; |
| 307 | |
| 308 | static const int eptype_to_xhci_out[] = { |
| 309 | [ USB_ENDPOINT_XFER_CONTROL] = 4, |
| 310 | [ USB_ENDPOINT_XFER_ISOC ] = 1, |
| 311 | [ USB_ENDPOINT_XFER_BULK ] = 2, |
| 312 | [ USB_ENDPOINT_XFER_INT ] = 3, |
| 313 | }; |
| 314 | |
| 315 | // -------------------------------------------------------------- |
| 316 | // internal functions, 16bit + 32bit |
| 317 | |
| 318 | static void xhci_doorbell(struct usb_xhci_s *xhci, u32 slotid, u32 value) |
| 319 | { |
| 320 | struct xhci_db *db = GET_LOWFLAT(xhci->db); |
| 321 | u32 addr = (u32)(&db[slotid].doorbell); |
| 322 | pci_writel(addr, value); |
| 323 | } |
| 324 | |
| 325 | static void xhci_process_events(struct usb_xhci_s *xhci) |
| 326 | { |
| 327 | struct xhci_ring *evts = GET_LOWFLAT(xhci->evts); |
| 328 | |
| 329 | for (;;) { |
| 330 | /* check for event */ |
| 331 | u32 nidx = GET_LOWFLAT(evts->nidx); |
| 332 | u32 cs = GET_LOWFLAT(evts->cs); |
| 333 | struct xhci_trb *etrb = evts->ring + nidx; |
| 334 | u32 control = GET_LOWFLAT(etrb->control); |
| 335 | if ((control & TRB_C) != (cs ? 1 : 0)) |
| 336 | return; |
| 337 | |
| 338 | /* process event */ |
| 339 | u32 evt_type = TRB_TYPE(control); |
| 340 | u32 evt_cc = (GET_LOWFLAT(etrb->status) >> 24) & 0xff; |
| 341 | switch (evt_type) { |
| 342 | case ER_TRANSFER: |
| 343 | case ER_COMMAND_COMPLETE: |
| 344 | { |
| 345 | struct xhci_trb *rtrb = (void*)GET_LOWFLAT(etrb->ptr_low); |
| 346 | struct xhci_ring *ring = XHCI_RING(rtrb); |
| 347 | struct xhci_trb *evt = &ring->evt; |
| 348 | u32 eidx = rtrb - ring->ring + 1; |
| 349 | dprintf(5, "%s: ring %p [trb %p, evt %p, type %d, eidx %d, cc %d]\n", |
| 350 | __func__, ring, rtrb, evt, evt_type, eidx, evt_cc); |
| 351 | memcpy_fl(evt, etrb, sizeof(*etrb)); |
| 352 | SET_LOWFLAT(ring->eidx, eidx); |
| 353 | break; |
| 354 | } |
| 355 | case ER_PORT_STATUS_CHANGE: |
| 356 | { |
| 357 | u32 portid = (GET_LOWFLAT(etrb->ptr_low) >> 24) & 0xff; |
| 358 | dprintf(3, "%s: status change port #%d\n", |
| 359 | __func__, portid); |
| 360 | break; |
| 361 | } |
| 362 | default: |
| 363 | dprintf(1, "%s: unknown event, type %d, cc %d\n", |
| 364 | __func__, evt_type, evt_cc); |
| 365 | break; |
| 366 | } |
| 367 | |
| 368 | /* move ring index, notify xhci */ |
| 369 | nidx++; |
| 370 | if (nidx == XHCI_RING_ITEMS) { |
| 371 | nidx = 0; |
| 372 | cs = cs ? 0 : 1; |
| 373 | SET_LOWFLAT(evts->cs, cs); |
| 374 | } |
| 375 | SET_LOWFLAT(evts->nidx, nidx); |
| 376 | struct xhci_ir *ir = GET_LOWFLAT(xhci->ir); |
| 377 | u32 addr = (u32)(&ir->erdp_low); |
| 378 | u32 erdp = (u32)(evts->ring + nidx); |
| 379 | pci_writel(addr, erdp); |
| 380 | } |
| 381 | } |
| 382 | |
| 383 | static int xhci_ring_busy(struct xhci_ring *ring) |
| 384 | { |
| 385 | u32 eidx = GET_LOWFLAT(ring->eidx); |
| 386 | u32 nidx = GET_LOWFLAT(ring->nidx); |
| 387 | return (eidx != nidx); |
| 388 | } |
| 389 | |
| 390 | static int xhci_event_wait(struct usb_xhci_s *xhci, |
| 391 | struct xhci_ring *ring, |
| 392 | u32 timeout) |
| 393 | { |
| 394 | u32 end = timer_calc(timeout); |
| 395 | |
| 396 | for (;;) { |
| 397 | xhci_process_events(xhci); |
| 398 | if (!xhci_ring_busy(ring)) { |
| 399 | u32 status = GET_LOWFLAT(ring->evt.status); |
| 400 | return (status >> 24) & 0xff; |
| 401 | } |
| 402 | if (timer_check(end)) { |
| 403 | warn_timeout(); |
| 404 | return -1; |
| 405 | } |
| 406 | yield(); |
| 407 | } |
| 408 | } |
| 409 | |
| 410 | static void xhci_trb_queue(struct xhci_ring *ring, |
| 411 | struct xhci_trb *trb) |
| 412 | { |
| 413 | u32 nidx = GET_LOWFLAT(ring->nidx); |
| 414 | u32 cs = GET_LOWFLAT(ring->cs); |
| 415 | struct xhci_trb *dst; |
| 416 | u32 control; |
| 417 | |
| 418 | if (nidx == XHCI_RING_ITEMS-1) { |
| 419 | dst = ring->ring + nidx; |
| 420 | control = (TR_LINK << 10); // trb type |
| 421 | control |= TRB_LK_TC; |
| 422 | control |= (cs ? TRB_C : 0); |
| 423 | SET_LOWFLAT(dst->ptr_low, (u32)&ring[0]); |
| 424 | SET_LOWFLAT(dst->ptr_high, 0); |
| 425 | SET_LOWFLAT(dst->status, 0); |
| 426 | SET_LOWFLAT(dst->control, control); |
| 427 | nidx = 0; |
| 428 | cs = cs ? 0 : 1; |
| 429 | SET_LOWFLAT(ring->nidx, nidx); |
| 430 | SET_LOWFLAT(ring->cs, cs); |
| 431 | |
| 432 | dprintf(5, "%s: ring %p [linked]\n", __func__, ring); |
| 433 | } |
| 434 | |
| 435 | dst = ring->ring + nidx; |
| 436 | control = GET_LOWFLAT(trb->control) | (cs ? TRB_C : 0); |
| 437 | |
| 438 | SET_LOWFLAT(dst->ptr_low, GET_LOWFLAT(trb->ptr_low)); |
| 439 | SET_LOWFLAT(dst->ptr_high, GET_LOWFLAT(trb->ptr_high)); |
| 440 | SET_LOWFLAT(dst->status, GET_LOWFLAT(trb->status)); |
| 441 | SET_LOWFLAT(dst->control, control); |
| 442 | nidx++; |
| 443 | SET_LOWFLAT(ring->nidx, nidx); |
| 444 | |
| 445 | dprintf(5, "%s: ring %p [nidx %d, len %d]\n", |
| 446 | __func__, ring, nidx, |
| 447 | GET_LOWFLAT(trb->status) & 0xffff); |
| 448 | } |
| 449 | |
| 450 | static void xhci_xfer_queue(struct xhci_pipe *pipe, |
| 451 | struct xhci_trb *trb) |
| 452 | { |
| 453 | xhci_trb_queue(&pipe->reqs, trb); |
| 454 | } |
| 455 | |
| 456 | static void xhci_xfer_kick(struct xhci_pipe *pipe) |
| 457 | { |
| 458 | struct xhci_device *dev = GET_LOWFLAT(pipe->dev); |
| 459 | struct usb_xhci_s *xhci = GET_LOWFLAT(dev->xhci); |
| 460 | u32 slotid = GET_LOWFLAT(dev->slotid); |
| 461 | u32 epid = GET_LOWFLAT(pipe->epid); |
| 462 | |
| 463 | dprintf(5, "%s: ring %p, slotid %d, epid %d\n", |
| 464 | __func__, &pipe->reqs, slotid, epid); |
| 465 | xhci_doorbell(xhci, slotid, epid); |
| 466 | } |
| 467 | |
| 468 | static void xhci_xfer_normal(struct xhci_pipe *pipe, |
| 469 | void *data, int datalen) |
| 470 | { |
| 471 | struct xhci_trb trb; |
| 472 | |
| 473 | memset(&trb, 0, sizeof(trb)); |
| 474 | trb.ptr_low = (u32)data; |
| 475 | trb.status = datalen; |
| 476 | trb.control |= (TR_NORMAL << 10); // trb type |
| 477 | trb.control |= TRB_TR_IOC; |
| 478 | |
| 479 | xhci_xfer_queue(pipe, MAKE_FLATPTR(GET_SEG(SS), &trb)); |
| 480 | xhci_xfer_kick(pipe); |
| 481 | } |
| 482 | |
| 483 | // -------------------------------------------------------------- |
| 484 | // internal functions, pure 32bit |
| 485 | |
| 486 | static int wait_bit(u32 *reg, u32 mask, int value, u32 timeout) |
| 487 | { |
| 488 | ASSERT32FLAT(); |
| 489 | u32 end = timer_calc(timeout); |
| 490 | |
| 491 | while ((readl(reg) & mask) != value) { |
| 492 | if (timer_check(end)) { |
| 493 | warn_timeout(); |
| 494 | return -1; |
| 495 | } |
| 496 | yield(); |
| 497 | } |
| 498 | return 0; |
| 499 | } |
| 500 | |
| 501 | static int xhci_cmd_submit(struct usb_xhci_s *xhci, |
| 502 | struct xhci_trb *cmd) |
| 503 | { |
| 504 | ASSERT32FLAT(); |
| 505 | int rc; |
| 506 | |
| 507 | mutex_lock(&xhci->cmds->lock); |
| 508 | xhci_trb_queue(xhci->cmds, cmd); |
| 509 | xhci_doorbell(xhci, 0, 0); |
| 510 | rc = xhci_event_wait(xhci, xhci->cmds, 1000); |
| 511 | mutex_unlock(&xhci->cmds->lock); |
| 512 | return rc; |
| 513 | } |
| 514 | |
| 515 | static int xhci_cmd_enable_slot(struct usb_xhci_s *xhci) |
| 516 | { |
| 517 | ASSERT32FLAT(); |
| 518 | struct xhci_trb cmd = { |
| 519 | .ptr_low = 0, |
| 520 | .ptr_high = 0, |
| 521 | .status = 0, |
| 522 | .control = (CR_ENABLE_SLOT << 10) |
| 523 | }; |
| 524 | dprintf(3, "%s:\n", __func__); |
| 525 | int cc = xhci_cmd_submit(xhci, &cmd); |
| 526 | if (cc != CC_SUCCESS) |
| 527 | return -1; |
| 528 | return (xhci->cmds->evt.control >> 24) & 0xff; |
| 529 | } |
| 530 | |
| 531 | static int xhci_cmd_disable_slot(struct xhci_device *dev) |
| 532 | { |
| 533 | ASSERT32FLAT(); |
| 534 | struct xhci_trb cmd = { |
| 535 | .ptr_low = 0, |
| 536 | .ptr_high = 0, |
| 537 | .status = 0, |
| 538 | .control = (dev->slotid << 24) | (CR_DISABLE_SLOT << 10) |
| 539 | }; |
| 540 | dprintf(3, "%s: slotid %d\n", __func__, dev->slotid); |
| 541 | return xhci_cmd_submit(dev->xhci, &cmd); |
| 542 | } |
| 543 | |
| 544 | static int xhci_cmd_address_device(struct xhci_device *dev) |
| 545 | { |
| 546 | ASSERT32FLAT(); |
| 547 | struct xhci_trb cmd = { |
| 548 | .ptr_low = (u32)&dev->inctx, |
| 549 | .ptr_high = 0, |
| 550 | .status = 0, |
| 551 | .control = (dev->slotid << 24) | (CR_ADDRESS_DEVICE << 10) |
| 552 | }; |
| 553 | dprintf(3, "%s: slotid %d\n", __func__, dev->slotid); |
| 554 | return xhci_cmd_submit(dev->xhci, &cmd); |
| 555 | } |
| 556 | |
| 557 | static int xhci_cmd_configure_endpoint(struct xhci_device *dev) |
| 558 | { |
| 559 | ASSERT32FLAT(); |
| 560 | struct xhci_trb cmd = { |
| 561 | .ptr_low = (u32)&dev->inctx, |
| 562 | .ptr_high = 0, |
| 563 | .status = 0, |
| 564 | .control = (dev->slotid << 24) | (CR_CONFIGURE_ENDPOINT << 10) |
| 565 | }; |
| 566 | dprintf(3, "%s: slotid %d, add 0x%x, del 0x%x\n", __func__, |
| 567 | dev->slotid, dev->inctx.add, dev->inctx.del); |
| 568 | return xhci_cmd_submit(dev->xhci, &cmd); |
| 569 | } |
| 570 | |
| 571 | static int xhci_cmd_evaluate_context(struct xhci_device *dev) |
| 572 | { |
| 573 | ASSERT32FLAT(); |
| 574 | struct xhci_trb cmd = { |
| 575 | .ptr_low = (u32)&dev->inctx, |
| 576 | .ptr_high = 0, |
| 577 | .status = 0, |
| 578 | .control = (dev->slotid << 24) | (CR_EVALUATE_CONTEXT << 10) |
| 579 | }; |
| 580 | dprintf(3, "%s: slotid %d, add 0x%x, del 0x%x\n", __func__, |
| 581 | dev->slotid, dev->inctx.add, dev->inctx.del); |
| 582 | return xhci_cmd_submit(dev->xhci, &cmd); |
| 583 | } |
| 584 | |
| 585 | static void xhci_xfer_setup(struct xhci_pipe *pipe, |
| 586 | const struct usb_ctrlrequest *req, |
| 587 | int dir, int datalen) |
| 588 | { |
| 589 | ASSERT32FLAT(); |
| 590 | struct xhci_trb trb; |
| 591 | |
| 592 | memset(&trb, 0, sizeof(trb)); |
| 593 | trb.ptr_low |= req->bRequestType; |
| 594 | trb.ptr_low |= (req->bRequest) << 8; |
| 595 | trb.ptr_low |= (req->wValue) << 16; |
| 596 | trb.ptr_high |= req->wIndex; |
| 597 | trb.ptr_high |= (req->wLength) << 16; |
| 598 | trb.status |= 8; // length |
| 599 | trb.control |= (TR_SETUP << 10); // trb type |
| 600 | trb.control |= TRB_TR_IDT; |
| 601 | if (datalen) |
| 602 | trb.control |= (dir ? 3 : 2) << 16; // transfer type |
| 603 | xhci_xfer_queue(pipe, &trb); |
| 604 | } |
| 605 | |
| 606 | static void xhci_xfer_data(struct xhci_pipe *pipe, |
| 607 | int dir, void *data, int datalen) |
| 608 | { |
| 609 | ASSERT32FLAT(); |
| 610 | struct xhci_trb trb; |
| 611 | |
| 612 | memset(&trb, 0, sizeof(trb)); |
| 613 | trb.ptr_low = (u32)data; |
| 614 | trb.status = datalen; |
| 615 | trb.control |= (TR_DATA << 10); // trb type |
| 616 | if (dir) |
| 617 | trb.control |= (1 << 16); |
| 618 | xhci_xfer_queue(pipe, &trb); |
| 619 | } |
| 620 | |
| 621 | static void xhci_xfer_status(struct xhci_pipe *pipe, int dir) |
| 622 | { |
| 623 | ASSERT32FLAT(); |
| 624 | struct xhci_trb trb; |
| 625 | |
| 626 | memset(&trb, 0, sizeof(trb)); |
| 627 | trb.control |= (TR_STATUS << 10); // trb type |
| 628 | trb.control |= TRB_TR_IOC; |
| 629 | if (dir) |
| 630 | trb.control |= (1 << 16); |
| 631 | |
| 632 | xhci_xfer_queue(pipe, &trb); |
| 633 | xhci_xfer_kick(pipe); |
| 634 | } |
| 635 | |
| 636 | static struct xhci_device *xhci_find_alloc_device(struct usb_xhci_s *xhci, |
| 637 | struct usbdevice_s *usbdev) |
| 638 | { |
| 639 | ASSERT32FLAT(); |
| 640 | struct xhci_device *dev; |
| 641 | |
| 642 | hlist_for_each_entry(dev, &xhci->list, next) { |
| 643 | if (dev->usbdev == usbdev) { |
| 644 | return dev; |
| 645 | } |
| 646 | } |
| 647 | |
| 648 | dev = memalign_low(64, sizeof(*dev)); |
| 649 | if (!dev) { |
| 650 | warn_noalloc(); |
| 651 | return NULL; |
| 652 | } |
| 653 | memset(dev, 0, sizeof(*dev)); |
| 654 | dev->usbdev = usbdev; |
| 655 | dev->xhci = xhci; |
| 656 | hlist_add_head(&dev->next, &xhci->list); |
| 657 | return dev; |
| 658 | } |
| 659 | |
| 660 | static void |
| 661 | configure_xhci(void *data) |
| 662 | { |
| 663 | ASSERT32FLAT(); |
| 664 | struct usb_xhci_s *xhci = data; |
| 665 | u32 reg; |
| 666 | |
| 667 | xhci->devs = memalign_high(64, sizeof(*xhci->devs) * (xhci->slots + 1)); |
| 668 | xhci->eseg = memalign_high(64, sizeof(*xhci->eseg)); |
| 669 | xhci->cmds = memalign_high(XHCI_RING_SIZE, sizeof(*xhci->cmds)); |
| 670 | xhci->evts = memalign_low(XHCI_RING_SIZE, sizeof(*xhci->evts)); |
| 671 | if (!xhci->devs || !xhci->cmds || !xhci->evts || !xhci->eseg) { |
| 672 | warn_noalloc(); |
| 673 | goto fail; |
| 674 | } |
| 675 | memset(xhci->devs, 0, sizeof(*xhci->devs) * (xhci->slots + 1)); |
| 676 | memset(xhci->cmds, 0, sizeof(*xhci->cmds)); |
| 677 | memset(xhci->evts, 0, sizeof(*xhci->evts)); |
| 678 | memset(xhci->eseg, 0, sizeof(*xhci->eseg)); |
| 679 | |
| 680 | reg = readl(&xhci->op->usbcmd); |
| 681 | if (reg & XHCI_CMD_RS) { |
| 682 | reg &= ~XHCI_CMD_RS; |
| 683 | writel(&xhci->op->usbcmd, reg); |
| 684 | if (wait_bit(&xhci->op->usbsts, XHCI_STS_HCH, XHCI_STS_HCH, 32) != 0) |
| 685 | goto fail; |
| 686 | } |
| 687 | |
| 688 | dprintf(3, "%s: resetting\n", __func__); |
| 689 | writel(&xhci->op->usbcmd, XHCI_CMD_HCRST); |
| 690 | if (wait_bit(&xhci->op->usbcmd, XHCI_CMD_HCRST, 0, 100) != 0) |
| 691 | goto fail; |
| 692 | if (wait_bit(&xhci->op->usbsts, XHCI_STS_CNR, 0, 100) != 0) |
| 693 | goto fail; |
| 694 | |
| 695 | writel(&xhci->op->config, xhci->slots); |
| 696 | writel(&xhci->op->dcbaap_low, (u32)xhci->devs); |
| 697 | writel(&xhci->op->dcbaap_high, 0); |
| 698 | writel(&xhci->op->crcr_low, (u32)xhci->cmds | 1); |
| 699 | writel(&xhci->op->crcr_high, 0); |
| 700 | xhci->cmds->cs = 1; |
| 701 | |
| 702 | xhci->eseg->ptr_low = (u32)xhci->evts; |
| 703 | xhci->eseg->ptr_high = 0; |
| 704 | xhci->eseg->size = XHCI_RING_ITEMS; |
| 705 | writel(&xhci->ir->erstsz, 1); |
| 706 | writel(&xhci->ir->erdp_low, (u32)xhci->evts); |
| 707 | writel(&xhci->ir->erdp_high, 0); |
| 708 | writel(&xhci->ir->erstba_low, (u32)xhci->eseg); |
| 709 | writel(&xhci->ir->erstba_high, 0); |
| 710 | xhci->evts->cs = 1; |
| 711 | |
| 712 | reg = readl(&xhci->op->usbcmd); |
| 713 | reg |= XHCI_CMD_RS; |
| 714 | writel(&xhci->op->usbcmd, reg); |
| 715 | |
| 716 | // FIXME: try find a more elegant way than a fixed delay |
| 717 | mdelay(100); |
| 718 | |
| 719 | usb_enumerate(&xhci->hub); |
| 720 | if (xhci->hub.devcount) |
| 721 | return; |
| 722 | |
| 723 | // No devices found - shutdown and free controller. |
| 724 | dprintf(1, "XHCI no devices found\n"); |
| 725 | reg = readl(&xhci->op->usbcmd); |
| 726 | reg &= ~XHCI_CMD_RS; |
| 727 | writel(&xhci->op->usbcmd, reg); |
| 728 | wait_bit(&xhci->op->usbsts, XHCI_STS_HCH, XHCI_STS_HCH, 32); |
| 729 | |
| 730 | fail: |
| 731 | free(xhci->eseg); |
| 732 | free(xhci->evts); |
| 733 | free(xhci->cmds); |
| 734 | free(xhci->devs); |
| 735 | free(xhci); |
| 736 | } |
| 737 | |
| 738 | // -------------------------------------------------------------- |
| 739 | // xhci root hub |
| 740 | |
| 741 | // Check if device attached to port |
| 742 | static void |
| 743 | xhci_print_port_state(int loglevel, const char *prefix, u32 port, u32 portsc) |
| 744 | { |
| 745 | ASSERT32FLAT(); |
| 746 | u32 pls = xhci_get_field(portsc, XHCI_PORTSC_PLS); |
| 747 | u32 speed = xhci_get_field(portsc, XHCI_PORTSC_SPEED); |
| 748 | |
| 749 | dprintf(loglevel, "%s port #%d: 0x%08x,%s%s pls %d, speed %d [%s]\n", |
| 750 | prefix, port + 1, portsc, |
| 751 | (portsc & XHCI_PORTSC_PP) ? " powered," : "", |
| 752 | (portsc & XHCI_PORTSC_PED) ? " enabled," : "", |
| 753 | pls, speed, speed_name[speed]); |
| 754 | } |
| 755 | |
| 756 | static int |
| 757 | xhci_hub_detect(struct usbhub_s *hub, u32 port) |
| 758 | { |
| 759 | ASSERT32FLAT(); |
| 760 | struct usb_xhci_s *xhci = container_of(hub->cntl, struct usb_xhci_s, usb); |
| 761 | u32 portsc = readl(&xhci->pr[port].portsc); |
| 762 | |
| 763 | xhci_print_port_state(3, __func__, port, portsc); |
| 764 | switch (xhci_get_field(portsc, XHCI_PORTSC_PLS)) { |
| 765 | case PLS_U0: |
| 766 | case PLS_POLLING: |
| 767 | return 0; |
| 768 | default: |
| 769 | return -1; |
| 770 | } |
| 771 | } |
| 772 | |
| 773 | // Reset device on port |
| 774 | static int |
| 775 | xhci_hub_reset(struct usbhub_s *hub, u32 port) |
| 776 | { |
| 777 | ASSERT32FLAT(); |
| 778 | struct usb_xhci_s *xhci = container_of(hub->cntl, struct usb_xhci_s, usb); |
| 779 | u32 portsc = readl(&xhci->pr[port].portsc); |
| 780 | int rc; |
| 781 | |
| 782 | switch (xhci_get_field(portsc, XHCI_PORTSC_PLS)) { |
| 783 | case PLS_U0: |
| 784 | rc = speed_from_xhci[xhci_get_field(portsc, XHCI_PORTSC_SPEED)]; |
| 785 | break; |
| 786 | case PLS_POLLING: |
| 787 | xhci_print_port_state(3, __func__, port, portsc); |
| 788 | portsc |= XHCI_PORTSC_PR; |
| 789 | writel(&xhci->pr[port].portsc, portsc); |
| 790 | if (wait_bit(&xhci->pr[port].portsc, XHCI_PORTSC_PED, XHCI_PORTSC_PED, 100) != 0) |
| 791 | return -1; |
| 792 | portsc = readl(&xhci->pr[port].portsc); |
| 793 | rc = speed_from_xhci[xhci_get_field(portsc, XHCI_PORTSC_SPEED)]; |
| 794 | break; |
| 795 | default: |
| 796 | rc = -1; |
| 797 | break; |
| 798 | } |
| 799 | |
| 800 | xhci_print_port_state(1, "XHCI", port, portsc); |
| 801 | return rc; |
| 802 | } |
| 803 | |
| 804 | static void |
| 805 | xhci_hub_disconnect(struct usbhub_s *hub, u32 port) |
| 806 | { |
| 807 | ASSERT32FLAT(); |
| 808 | struct usb_xhci_s *xhci = container_of(hub->cntl, struct usb_xhci_s, usb); |
| 809 | struct xhci_device *dev; |
| 810 | |
| 811 | hlist_for_each_entry(dev, &xhci->list, next) { |
| 812 | if (dev->usbdev->hub == hub && |
| 813 | dev->usbdev->port == port && |
| 814 | dev->slotid != 0) { |
| 815 | xhci_cmd_disable_slot(dev); |
| 816 | hlist_del(&dev->next); |
| 817 | return; |
| 818 | } |
| 819 | } |
| 820 | } |
| 821 | |
| 822 | static struct usbhub_op_s xhci_hub_ops = { |
| 823 | .detect = xhci_hub_detect, |
| 824 | .reset = xhci_hub_reset, |
| 825 | .disconnect = xhci_hub_disconnect, |
| 826 | }; |
| 827 | |
| 828 | // -------------------------------------------------------------- |
| 829 | // external interface |
| 830 | |
| 831 | struct usb_pipe * |
| 832 | xhci_alloc_pipe(struct usbdevice_s *usbdev |
| 833 | , struct usb_endpoint_descriptor *epdesc) |
| 834 | { |
| 835 | ASSERT32FLAT(); |
| 836 | if (!CONFIG_USB_XHCI) |
| 837 | return NULL; |
| 838 | u8 eptype = epdesc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
| 839 | struct usb_xhci_s *xhci = container_of( |
| 840 | usbdev->hub->cntl, struct usb_xhci_s, usb); |
| 841 | struct xhci_pipe *pipe; |
| 842 | u32 epid; |
| 843 | |
| 844 | if (epdesc->bEndpointAddress == 0) { |
| 845 | epid = 1; |
| 846 | } else { |
| 847 | epid = (epdesc->bEndpointAddress & 0x0f) * 2; |
| 848 | epid += (epdesc->bEndpointAddress & USB_DIR_IN) ? 1 : 0; |
| 849 | } |
| 850 | |
| 851 | if (eptype == USB_ENDPOINT_XFER_CONTROL) |
| 852 | pipe = memalign_high(XHCI_RING_SIZE, sizeof(*pipe)); |
| 853 | else |
| 854 | pipe = memalign_low(XHCI_RING_SIZE, sizeof(*pipe)); |
| 855 | if (!pipe) { |
| 856 | warn_noalloc(); |
| 857 | return NULL; |
| 858 | } |
| 859 | memset(pipe, 0, sizeof(*pipe)); |
| 860 | |
| 861 | usb_desc2pipe(&pipe->pipe, usbdev, epdesc); |
| 862 | pipe->dev = xhci_find_alloc_device(xhci, usbdev); |
| 863 | if (!pipe->dev) { |
| 864 | free(pipe); |
| 865 | return NULL; |
| 866 | } |
| 867 | pipe->epid = epid; |
| 868 | pipe->reqs.cs = 1; |
| 869 | if (eptype == USB_ENDPOINT_XFER_INT) |
| 870 | pipe->buf = malloc_low(pipe->pipe.maxpacket); |
| 871 | |
| 872 | dprintf(3, "%s: usbdev %p, ring %p, slotid %d, epid %d\n", __func__, |
| 873 | usbdev, &pipe->reqs, pipe->dev->slotid, pipe->epid); |
| 874 | if (pipe->epid > 1 && pipe->dev->slotid) { |
| 875 | struct xhci_inctx *in = &pipe->dev->inctx; |
| 876 | in->add = (1 << pipe->epid) | 1; |
| 877 | in->del = 0; |
| 878 | |
| 879 | in->slot.ctx[0] |= (31 << 27); // context entries |
| 880 | |
| 881 | int e = pipe->epid-1; |
| 882 | in->ep[e].ctx[1] |= (eptype << 3); |
| 883 | if (epdesc->bEndpointAddress & USB_DIR_IN) |
| 884 | in->ep[e].ctx[1] |= (1 << 5); |
| 885 | in->ep[e].ctx[1] |= (pipe->pipe.maxpacket << 16); |
| 886 | in->ep[e].deq_low = (u32)&pipe->reqs.ring[0]; |
| 887 | in->ep[e].deq_low |= 1; // dcs |
| 888 | in->ep[e].deq_high = 0; |
| 889 | in->ep[e].length = pipe->pipe.maxpacket; |
| 890 | |
| 891 | int cc = xhci_cmd_configure_endpoint(pipe->dev); |
| 892 | if (cc != CC_SUCCESS) { |
| 893 | dprintf(1, "%s: configure endpoint: failed (cc %d)\n", __func__, cc); |
| 894 | free(pipe); |
| 895 | return NULL; |
| 896 | } |
| 897 | } |
| 898 | |
| 899 | return &pipe->pipe; |
| 900 | } |
| 901 | |
| 902 | struct usb_pipe * |
| 903 | xhci_update_pipe(struct usbdevice_s *usbdev, struct usb_pipe *upipe |
| 904 | , struct usb_endpoint_descriptor *epdesc) |
| 905 | { |
| 906 | ASSERT32FLAT(); |
| 907 | if (!CONFIG_USB_XHCI) |
| 908 | return NULL; |
| 909 | u8 eptype = epdesc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
| 910 | struct xhci_pipe *pipe = container_of(upipe, struct xhci_pipe, pipe); |
| 911 | dprintf(3, "%s: usbdev %p, ring %p, slotid %d, epid %d\n", __func__, |
| 912 | usbdev, &pipe->reqs, pipe->dev->slotid, pipe->epid); |
| 913 | if (eptype == USB_ENDPOINT_XFER_CONTROL && |
| 914 | pipe->pipe.maxpacket != epdesc->wMaxPacketSize) { |
| 915 | dprintf(1, "%s: reconf ctl endpoint pkt size: %d -> %d\n", |
| 916 | __func__, pipe->pipe.maxpacket, epdesc->wMaxPacketSize); |
| 917 | pipe->pipe.maxpacket = epdesc->wMaxPacketSize; |
| 918 | struct xhci_inctx *in = &pipe->dev->inctx; |
| 919 | in->add = (1 << 1); |
| 920 | in->del = 0; |
| 921 | in->ep[0].ctx[1] &= 0xffff; |
| 922 | in->ep[0].ctx[1] |= (pipe->pipe.maxpacket << 16); |
| 923 | int cc = xhci_cmd_evaluate_context(pipe->dev); |
| 924 | if (cc != CC_SUCCESS) { |
| 925 | dprintf(1, "%s: reconf ctl endpoint: failed (cc %d)\n", |
| 926 | __func__, cc); |
| 927 | } |
| 928 | } |
| 929 | return upipe; |
| 930 | } |
| 931 | |
| 932 | int |
| 933 | xhci_control(struct usb_pipe *p, int dir, const void *cmd, int cmdsize |
| 934 | , void *data, int datalen) |
| 935 | { |
| 936 | ASSERT32FLAT(); |
| 937 | if (!CONFIG_USB_XHCI) |
| 938 | return -1; |
| 939 | const struct usb_ctrlrequest *req = cmd; |
| 940 | struct xhci_pipe *pipe = container_of(p, struct xhci_pipe, pipe); |
| 941 | struct usb_xhci_s *xhci = pipe->dev->xhci; |
| 942 | int cc; |
| 943 | |
| 944 | if (req->bRequest == USB_REQ_SET_ADDRESS) { |
| 945 | int slotid = xhci_cmd_enable_slot(xhci); |
| 946 | if (slotid < 0) { |
| 947 | dprintf(1, "%s: enable slot: failed\n", __func__); |
| 948 | return -1; |
| 949 | } |
| 950 | dprintf(3, "%s: enable slot: got slotid %d\n", __func__, slotid); |
| 951 | pipe->dev->slotid = slotid; |
| 952 | xhci->devs[slotid].ptr_low = (u32)&pipe->dev->devctx; |
| 953 | xhci->devs[slotid].ptr_high = 0; |
| 954 | |
| 955 | struct usbdevice_s *usbdev = pipe->dev->usbdev; |
| 956 | u32 route = 0; |
| 957 | while (usbdev->hub->usbdev) { |
| 958 | route <<= 4; |
| 959 | route |= (usbdev->port+1) & 0xf; |
| 960 | usbdev = usbdev->hub->usbdev; |
| 961 | } |
| 962 | dprintf(3, "%s: root port %d, route 0x%x\n", |
| 963 | __func__, usbdev->port+1, route); |
| 964 | |
| 965 | struct xhci_inctx *in = &pipe->dev->inctx; |
| 966 | in->add = 0x03; |
| 967 | in->slot.ctx[0] |= (1 << 27); // context entries |
| 968 | in->slot.ctx[0] |= speed_to_xhci[pipe->dev->usbdev->speed] << 20; |
| 969 | in->slot.ctx[0] |= route; |
| 970 | in->slot.ctx[1] |= (usbdev->port+1) << 16; |
| 971 | /* TODO ctx0: hub bit */ |
| 972 | /* TODO ctx1: hub ports */ |
| 973 | |
| 974 | in->ep[0].ctx[0] |= (3 << 16); // interval: 1ms |
| 975 | in->ep[0].ctx[1] |= (4 << 3); // control pipe |
| 976 | in->ep[0].ctx[1] |= (speed_to_ctlsize[pipe->dev->usbdev->speed] << 16); |
| 977 | |
| 978 | in->ep[0].deq_low = (u32)&pipe->reqs.ring[0]; |
| 979 | in->ep[0].deq_low |= 1; // dcs |
| 980 | in->ep[0].deq_high = 0; |
| 981 | in->ep[0].length = 8; |
| 982 | |
| 983 | cc = xhci_cmd_address_device(pipe->dev); |
| 984 | if (cc != CC_SUCCESS) { |
| 985 | dprintf(1, "%s: address device: failed (cc %d)\n", __func__, cc); |
| 986 | return -1; |
| 987 | } |
| 988 | return 0; |
| 989 | } |
| 990 | |
| 991 | xhci_xfer_setup(pipe, req, dir, datalen); |
| 992 | if (datalen) |
| 993 | xhci_xfer_data(pipe, dir, data, datalen); |
| 994 | xhci_xfer_status(pipe, dir); |
| 995 | |
| 996 | cc = xhci_event_wait(xhci, &pipe->reqs, 1000); |
| 997 | if (cc != CC_SUCCESS) { |
| 998 | dprintf(1, "%s: control xfer failed (cc %d)\n", __func__, cc); |
| 999 | return -1; |
| 1000 | } |
| 1001 | |
| 1002 | return 0; |
| 1003 | } |
| 1004 | |
| 1005 | int |
| 1006 | xhci_send_bulk(struct usb_pipe *p, int dir, void *data, int datalen) |
| 1007 | { |
| 1008 | if (!CONFIG_USB_XHCI) |
| 1009 | return -1; |
| 1010 | |
| 1011 | struct xhci_pipe *pipe = container_of(p, struct xhci_pipe, pipe); |
| 1012 | struct xhci_device *dev = GET_LOWFLAT(pipe->dev); |
| 1013 | struct usb_xhci_s *xhci = GET_LOWFLAT(dev->xhci); |
| 1014 | |
| 1015 | xhci_xfer_normal(pipe, data, datalen); |
| 1016 | int cc = xhci_event_wait(xhci, &pipe->reqs, 1000); |
| 1017 | if (cc != CC_SUCCESS) { |
| 1018 | dprintf(1, "%s: bulk xfer failed (cc %d)\n", __func__, cc); |
| 1019 | return -1; |
| 1020 | } |
| 1021 | return 0; |
| 1022 | } |
| 1023 | |
| 1024 | int |
| 1025 | xhci_poll_intr(struct usb_pipe *p, void *data) |
| 1026 | { |
| 1027 | if (!CONFIG_USB_XHCI) |
| 1028 | return -1; |
| 1029 | |
| 1030 | struct xhci_pipe *pipe = container_of(p, struct xhci_pipe, pipe); |
| 1031 | struct xhci_device *dev = GET_LOWFLAT(pipe->dev); |
| 1032 | struct usb_xhci_s *xhci = GET_LOWFLAT(dev->xhci); |
| 1033 | u32 len = GET_LOWFLAT(pipe->pipe.maxpacket); |
| 1034 | void *buf = GET_LOWFLAT(pipe->buf); |
| 1035 | int bufused = GET_LOWFLAT(pipe->bufused); |
| 1036 | |
| 1037 | if (!bufused) { |
| 1038 | xhci_xfer_normal(pipe, buf, len); |
| 1039 | bufused = 1; |
| 1040 | SET_LOWFLAT(pipe->bufused, bufused); |
| 1041 | return -1; |
| 1042 | } |
| 1043 | |
| 1044 | xhci_process_events(xhci); |
| 1045 | if (xhci_ring_busy(&pipe->reqs)) |
| 1046 | return -1; |
| 1047 | dprintf(5, "%s: st %x ct %x [ %p <= %p / %d ]\n", __func__, |
| 1048 | GET_LOWFLAT(pipe->reqs.evt.status), |
| 1049 | GET_LOWFLAT(pipe->reqs.evt.control), |
| 1050 | MAKE_FLATPTR(GET_SEG(SS), data), buf, len); |
| 1051 | memcpy_fl(MAKE_FLATPTR(GET_SEG(SS), data), buf, len); |
| 1052 | xhci_xfer_normal(pipe, buf, len); |
| 1053 | return 0; |
| 1054 | } |
| 1055 | |
| 1056 | int |
| 1057 | xhci_setup(struct pci_device *pci, int busid) |
| 1058 | { |
| 1059 | ASSERT32FLAT(); |
| 1060 | if (!CONFIG_USB_XHCI) |
| 1061 | return -1; |
| 1062 | |
| 1063 | struct usb_xhci_s *xhci = malloc_low(sizeof(*xhci)); |
| 1064 | if (!xhci) { |
| 1065 | warn_noalloc(); |
| 1066 | return -1; |
| 1067 | } |
| 1068 | memset(xhci, 0, sizeof(*xhci)); |
| 1069 | |
| 1070 | xhci->baseaddr = pci_config_readl(pci->bdf, PCI_BASE_ADDRESS_0) |
| 1071 | & PCI_BASE_ADDRESS_MEM_MASK; |
| 1072 | xhci->caps = (void*)(xhci->baseaddr); |
| 1073 | xhci->op = (void*)(xhci->baseaddr + readb(&xhci->caps->caplength)); |
| 1074 | xhci->pr = (void*)(xhci->baseaddr + readb(&xhci->caps->caplength) + 0x400); |
| 1075 | xhci->db = (void*)(xhci->baseaddr + readl(&xhci->caps->dboff)); |
| 1076 | xhci->ir = (void*)(xhci->baseaddr + readl(&xhci->caps->rtsoff) + 0x20); |
| 1077 | |
| 1078 | u32 hcs1 = readl(&xhci->caps->hcsparams1); |
| 1079 | u32 hcc = readl(&xhci->caps->hccparams); |
| 1080 | xhci->ports = (hcs1 >> 24) & 0xff; |
| 1081 | xhci->slots = hcs1 & 0xff; |
| 1082 | xhci->xcap = ((hcc >> 16) & 0xffff) << 2; |
| 1083 | |
| 1084 | xhci->usb.busid = busid; |
| 1085 | xhci->usb.pci = pci; |
| 1086 | xhci->usb.type = USB_TYPE_XHCI; |
| 1087 | xhci->hub.cntl = &xhci->usb; |
| 1088 | xhci->hub.portcount = xhci->ports; |
| 1089 | xhci->hub.op = &xhci_hub_ops; |
| 1090 | |
| 1091 | dprintf(1, "XHCI init on dev %02x:%02x.%x: regs @ %p, %d ports, %d slots\n" |
| 1092 | , pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf) |
| 1093 | , pci_bdf_to_fn(pci->bdf), xhci->caps |
| 1094 | , xhci->ports, xhci->slots); |
| 1095 | |
| 1096 | if (xhci->xcap) { |
| 1097 | u32 off, addr = xhci->baseaddr + xhci->xcap; |
| 1098 | do { |
| 1099 | struct xhci_xcap *xcap = (void*)addr; |
| 1100 | u32 ports, name, cap = readl(&xcap->cap); |
| 1101 | switch (cap & 0xff) { |
| 1102 | case 0x02: |
| 1103 | name = readl(&xcap->data[0]); |
| 1104 | ports = readl(&xcap->data[1]); |
| 1105 | dprintf(1, "XHCI protocol %c%c%c%c %x.%02x, %d ports (offset %d)\n" |
| 1106 | , (name >> 0) & 0xff |
| 1107 | , (name >> 8) & 0xff |
| 1108 | , (name >> 16) & 0xff |
| 1109 | , (name >> 24) & 0xff |
| 1110 | , (cap >> 24) & 0xff |
| 1111 | , (cap >> 16) & 0xff |
| 1112 | , (ports >> 8) & 0xff |
| 1113 | , (ports >> 0) & 0xff); |
| 1114 | break; |
| 1115 | default: |
| 1116 | dprintf(1, "XHCI extcap 0x%x @ %x\n", cap & 0xff, addr); |
| 1117 | break; |
| 1118 | } |
| 1119 | off = (cap >> 8) & 0xff; |
| 1120 | addr += off << 2; |
| 1121 | } while (off > 0); |
| 1122 | } |
| 1123 | |
| 1124 | pci_config_maskw(pci->bdf, PCI_COMMAND, 0, PCI_COMMAND_MASTER); |
| 1125 | |
| 1126 | run_thread(configure_xhci, xhci); |
| 1127 | return 0; |
| 1128 | } |