blob: b370d1afb88d8cc0b3dde75eb9cdd13c5298e5b7 [file] [log] [blame]
Kevin O'Connor3471fdb2012-01-14 19:02:43 -05001// Standard VGA IO port access
2//
3// Copyright (C) 2012 Kevin O'Connor <kevin@koconnor.net>
4//
5// This file may be distributed under the terms of the GNU LGPLv3 license.
6
7#include "stdvga.h" // stdvga_pelmask_read
Kevin O'Connorf98bbf02012-01-27 23:09:02 -05008#include "farptr.h" // GET_FARVAR
Kevin O'Connor3471fdb2012-01-14 19:02:43 -05009#include "ioport.h" // inb
10
11u8
12stdvga_pelmask_read(void)
13{
14 return inb(VGAREG_PEL_MASK);
15}
16
17void
18stdvga_pelmask_write(u8 value)
19{
20 outb(value, VGAREG_PEL_MASK);
21}
22
23
24u8
25stdvga_misc_read(void)
26{
27 return inb(VGAREG_READ_MISC_OUTPUT);
28}
29
30void
31stdvga_misc_write(u8 value)
32{
33 outb(value, VGAREG_WRITE_MISC_OUTPUT);
34}
35
36void
37stdvga_misc_mask(u8 off, u8 on)
38{
39 stdvga_misc_write((stdvga_misc_read() & ~off) | on);
40}
41
42
43u8
44stdvga_sequ_read(u8 index)
45{
46 outb(index, VGAREG_SEQU_ADDRESS);
47 return inb(VGAREG_SEQU_DATA);
48}
49
50void
51stdvga_sequ_write(u8 index, u8 value)
52{
53 outw((value<<8) | index, VGAREG_SEQU_ADDRESS);
54}
55
56void
57stdvga_sequ_mask(u8 index, u8 off, u8 on)
58{
59 outb(index, VGAREG_SEQU_ADDRESS);
60 u8 v = inb(VGAREG_SEQU_DATA);
61 outb((v & ~off) | on, VGAREG_SEQU_DATA);
62}
63
64
65u8
66stdvga_grdc_read(u8 index)
67{
68 outb(index, VGAREG_GRDC_ADDRESS);
69 return inb(VGAREG_GRDC_DATA);
70}
71
72void
73stdvga_grdc_write(u8 index, u8 value)
74{
75 outw((value<<8) | index, VGAREG_GRDC_ADDRESS);
76}
77
78void
79stdvga_grdc_mask(u8 index, u8 off, u8 on)
80{
81 outb(index, VGAREG_GRDC_ADDRESS);
82 u8 v = inb(VGAREG_GRDC_DATA);
83 outb((v & ~off) | on, VGAREG_GRDC_DATA);
84}
85
86
87u8
88stdvga_crtc_read(u16 crtc_addr, u8 index)
89{
90 outb(index, crtc_addr);
91 return inb(crtc_addr + 1);
92}
93
94void
95stdvga_crtc_write(u16 crtc_addr, u8 index, u8 value)
96{
97 outw((value<<8) | index, crtc_addr);
98}
99
100void
101stdvga_crtc_mask(u16 crtc_addr, u8 index, u8 off, u8 on)
102{
103 outb(index, crtc_addr);
104 u8 v = inb(crtc_addr + 1);
105 outb((v & ~off) | on, crtc_addr + 1);
106}
107
108
109u8
110stdvga_attr_read(u8 index)
111{
112 inb(VGAREG_ACTL_RESET);
113 u8 orig = inb(VGAREG_ACTL_ADDRESS);
114 outb(index, VGAREG_ACTL_ADDRESS);
115 u8 v = inb(VGAREG_ACTL_READ_DATA);
116 inb(VGAREG_ACTL_RESET);
117 outb(orig, VGAREG_ACTL_ADDRESS);
118 return v;
119}
120
121void
122stdvga_attr_write(u8 index, u8 value)
123{
124 inb(VGAREG_ACTL_RESET);
125 u8 orig = inb(VGAREG_ACTL_ADDRESS);
126 outb(index, VGAREG_ACTL_ADDRESS);
127 outb(value, VGAREG_ACTL_WRITE_DATA);
128 outb(orig, VGAREG_ACTL_ADDRESS);
129}
130
131void
132stdvga_attr_mask(u8 index, u8 off, u8 on)
133{
134 inb(VGAREG_ACTL_RESET);
135 u8 orig = inb(VGAREG_ACTL_ADDRESS);
136 outb(index, VGAREG_ACTL_ADDRESS);
137 u8 v = inb(VGAREG_ACTL_READ_DATA);
138 outb((v & ~off) | on, VGAREG_ACTL_WRITE_DATA);
139 outb(orig, VGAREG_ACTL_ADDRESS);
140}
141
142u8
143stdvga_attrindex_read(void)
144{
145 inb(VGAREG_ACTL_RESET);
146 return inb(VGAREG_ACTL_ADDRESS);
147}
148
149void
150stdvga_attrindex_write(u8 value)
151{
152 inb(VGAREG_ACTL_RESET);
153 outb(value, VGAREG_ACTL_ADDRESS);
154}
155
156
157void
158stdvga_dac_read(u16 seg, u8 *data_far, u8 start, int count)
159{
160 outb(start, VGAREG_DAC_READ_ADDRESS);
161 while (count) {
162 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
163 data_far++;
164 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
165 data_far++;
166 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
167 data_far++;
168 count--;
169 }
170}
171
172void
173stdvga_dac_write(u16 seg, u8 *data_far, u8 start, int count)
174{
175 outb(start, VGAREG_DAC_WRITE_ADDRESS);
176 while (count) {
177 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
178 data_far++;
179 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
180 data_far++;
181 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
182 data_far++;
183 count--;
184 }
185}