Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 1 | // VGA io port access |
| 2 | // |
| 3 | // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net> |
| 4 | // Copyright (C) 2001-2008 the LGPL VGABios developers Team |
| 5 | // |
| 6 | // This file may be distributed under the terms of the GNU LGPLv3 license. |
| 7 | |
| 8 | #include "ioport.h" // outb |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 9 | #include "farptr.h" // SET_FARVAR |
Kevin O'Connor | a0ecb05 | 2009-05-18 23:34:00 -0400 | [diff] [blame] | 10 | #include "biosvar.h" // GET_BDA |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 11 | #include "vgatables.h" // VGAREG_* |
| 12 | |
| 13 | |
| 14 | /**************************************************************** |
| 15 | * Attribute control |
| 16 | ****************************************************************/ |
| 17 | |
| 18 | void |
Kevin O'Connor | a0ecb05 | 2009-05-18 23:34:00 -0400 | [diff] [blame] | 19 | vgahw_screen_disable() |
| 20 | { |
| 21 | inb(VGAREG_ACTL_RESET); |
| 22 | outb(0x00, VGAREG_ACTL_ADDRESS); |
| 23 | } |
| 24 | |
| 25 | void |
| 26 | vgahw_screen_enable() |
| 27 | { |
| 28 | inb(VGAREG_ACTL_RESET); |
| 29 | outb(0x20, VGAREG_ACTL_ADDRESS); |
| 30 | } |
| 31 | |
| 32 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 33 | vgahw_set_border_color(u8 color) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 34 | { |
| 35 | inb(VGAREG_ACTL_RESET); |
| 36 | outb(0x00, VGAREG_ACTL_ADDRESS); |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 37 | u8 v1 = color & 0x0f; |
| 38 | if (v1 & 0x08) |
| 39 | v1 += 0x08; |
| 40 | outb(v1, VGAREG_ACTL_WRITE_DATA); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 41 | |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 42 | u8 v2 = color & 0x10; |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 43 | int i; |
| 44 | for (i = 1; i < 4; i++) { |
| 45 | outb(i, VGAREG_ACTL_ADDRESS); |
| 46 | |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 47 | u8 cur = inb(VGAREG_ACTL_READ_DATA); |
| 48 | cur &= 0xef; |
| 49 | cur |= v2; |
| 50 | outb(cur, VGAREG_ACTL_WRITE_DATA); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 51 | } |
| 52 | outb(0x20, VGAREG_ACTL_ADDRESS); |
| 53 | } |
| 54 | |
| 55 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 56 | vgahw_set_overscan_border_color(u8 color) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 57 | { |
| 58 | inb(VGAREG_ACTL_RESET); |
| 59 | outb(0x11, VGAREG_ACTL_ADDRESS); |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 60 | outb(color, VGAREG_ACTL_WRITE_DATA); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 61 | outb(0x20, VGAREG_ACTL_ADDRESS); |
| 62 | } |
| 63 | |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 64 | u8 |
| 65 | vgahw_get_overscan_border_color() |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 66 | { |
| 67 | inb(VGAREG_ACTL_RESET); |
| 68 | outb(0x11, VGAREG_ACTL_ADDRESS); |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 69 | u8 v = inb(VGAREG_ACTL_READ_DATA); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 70 | inb(VGAREG_ACTL_RESET); |
| 71 | outb(0x20, VGAREG_ACTL_ADDRESS); |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 72 | return v; |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 76 | vgahw_set_palette(u8 palid) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 77 | { |
| 78 | inb(VGAREG_ACTL_RESET); |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 79 | palid &= 0x01; |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 80 | int i; |
| 81 | for (i = 1; i < 4; i++) { |
| 82 | outb(i, VGAREG_ACTL_ADDRESS); |
| 83 | |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 84 | u8 v = inb(VGAREG_ACTL_READ_DATA); |
| 85 | v &= 0xfe; |
| 86 | v |= palid; |
| 87 | outb(v, VGAREG_ACTL_WRITE_DATA); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 88 | } |
| 89 | outb(0x20, VGAREG_ACTL_ADDRESS); |
| 90 | } |
| 91 | |
| 92 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 93 | vgahw_set_single_palette_reg(u8 reg, u8 val) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 94 | { |
| 95 | inb(VGAREG_ACTL_RESET); |
| 96 | outb(reg, VGAREG_ACTL_ADDRESS); |
| 97 | outb(val, VGAREG_ACTL_WRITE_DATA); |
| 98 | outb(0x20, VGAREG_ACTL_ADDRESS); |
| 99 | } |
| 100 | |
| 101 | u8 |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 102 | vgahw_get_single_palette_reg(u8 reg) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 103 | { |
| 104 | inb(VGAREG_ACTL_RESET); |
| 105 | outb(reg, VGAREG_ACTL_ADDRESS); |
| 106 | u8 v = inb(VGAREG_ACTL_READ_DATA); |
| 107 | inb(VGAREG_ACTL_RESET); |
| 108 | outb(0x20, VGAREG_ACTL_ADDRESS); |
| 109 | return v; |
| 110 | } |
| 111 | |
| 112 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 113 | vgahw_set_all_palette_reg(u16 seg, u8 *data_far) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 114 | { |
| 115 | inb(VGAREG_ACTL_RESET); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 116 | int i; |
| 117 | for (i = 0; i < 0x10; i++) { |
| 118 | outb(i, VGAREG_ACTL_ADDRESS); |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 119 | u8 val = GET_FARVAR(seg, *data_far); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 120 | outb(val, VGAREG_ACTL_WRITE_DATA); |
| 121 | data_far++; |
| 122 | } |
| 123 | outb(0x11, VGAREG_ACTL_ADDRESS); |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 124 | outb(GET_FARVAR(seg, *data_far), VGAREG_ACTL_WRITE_DATA); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 125 | outb(0x20, VGAREG_ACTL_ADDRESS); |
| 126 | } |
| 127 | |
| 128 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 129 | vgahw_get_all_palette_reg(u16 seg, u8 *data_far) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 130 | { |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 131 | int i; |
| 132 | for (i = 0; i < 0x10; i++) { |
| 133 | inb(VGAREG_ACTL_RESET); |
| 134 | outb(i, VGAREG_ACTL_ADDRESS); |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 135 | SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA)); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 136 | data_far++; |
| 137 | } |
| 138 | inb(VGAREG_ACTL_RESET); |
| 139 | outb(0x11, VGAREG_ACTL_ADDRESS); |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 140 | SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA)); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 141 | inb(VGAREG_ACTL_RESET); |
| 142 | outb(0x20, VGAREG_ACTL_ADDRESS); |
| 143 | } |
| 144 | |
| 145 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 146 | vgahw_toggle_intensity(u8 flag) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 147 | { |
| 148 | inb(VGAREG_ACTL_RESET); |
| 149 | outb(0x10, VGAREG_ACTL_ADDRESS); |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 150 | u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0xf7) | ((flag & 0x01) << 3); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 151 | outb(val, VGAREG_ACTL_WRITE_DATA); |
| 152 | outb(0x20, VGAREG_ACTL_ADDRESS); |
| 153 | } |
| 154 | |
| 155 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 156 | vgahw_select_video_dac_color_page(u8 flag, u8 data) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 157 | { |
| 158 | inb(VGAREG_ACTL_RESET); |
| 159 | outb(0x10, VGAREG_ACTL_ADDRESS); |
| 160 | u8 val = inb(VGAREG_ACTL_READ_DATA); |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 161 | if (!(flag & 0x01)) { |
| 162 | // select paging mode |
| 163 | val = (val & 0x7f) | (data << 7); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 164 | outb(val, VGAREG_ACTL_WRITE_DATA); |
| 165 | outb(0x20, VGAREG_ACTL_ADDRESS); |
| 166 | return; |
| 167 | } |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 168 | // select page |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 169 | inb(VGAREG_ACTL_RESET); |
| 170 | outb(0x14, VGAREG_ACTL_ADDRESS); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 171 | if (!(val & 0x80)) |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 172 | data <<= 2; |
| 173 | data &= 0x0f; |
| 174 | outb(data, VGAREG_ACTL_WRITE_DATA); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 175 | outb(0x20, VGAREG_ACTL_ADDRESS); |
| 176 | } |
| 177 | |
| 178 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 179 | vgahw_read_video_dac_state(u8 *pmode, u8 *curpage) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 180 | { |
| 181 | inb(VGAREG_ACTL_RESET); |
| 182 | outb(0x10, VGAREG_ACTL_ADDRESS); |
| 183 | u8 val1 = inb(VGAREG_ACTL_READ_DATA) >> 7; |
| 184 | |
| 185 | inb(VGAREG_ACTL_RESET); |
| 186 | outb(0x14, VGAREG_ACTL_ADDRESS); |
| 187 | u8 val2 = inb(VGAREG_ACTL_READ_DATA) & 0x0f; |
| 188 | if (!(val1 & 0x01)) |
| 189 | val2 >>= 2; |
| 190 | |
| 191 | inb(VGAREG_ACTL_RESET); |
| 192 | outb(0x20, VGAREG_ACTL_ADDRESS); |
| 193 | |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 194 | *pmode = val1; |
| 195 | *curpage = val2; |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | |
| 199 | /**************************************************************** |
| 200 | * DAC control |
| 201 | ****************************************************************/ |
| 202 | |
| 203 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 204 | vgahw_set_dac_regs(u16 seg, u8 *data_far, u8 start, int count) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 205 | { |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 206 | outb(start, VGAREG_DAC_WRITE_ADDRESS); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 207 | while (count) { |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 208 | outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 209 | data_far++; |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 210 | outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 211 | data_far++; |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 212 | outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 213 | data_far++; |
| 214 | count--; |
| 215 | } |
| 216 | } |
| 217 | |
| 218 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 219 | vgahw_get_dac_regs(u16 seg, u8 *data_far, u8 start, int count) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 220 | { |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 221 | outb(start, VGAREG_DAC_READ_ADDRESS); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 222 | while (count) { |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 223 | SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 224 | data_far++; |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 225 | SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 226 | data_far++; |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 227 | SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 228 | data_far++; |
| 229 | count--; |
| 230 | } |
| 231 | } |
| 232 | |
| 233 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 234 | vgahw_set_pel_mask(u8 val) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 235 | { |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 236 | outb(val, VGAREG_PEL_MASK); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 237 | } |
| 238 | |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 239 | u8 |
| 240 | vgahw_get_pel_mask() |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 241 | { |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 242 | return inb(VGAREG_PEL_MASK); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 243 | } |
| 244 | |
Kevin O'Connor | ca66864 | 2009-05-21 23:06:08 -0400 | [diff] [blame] | 245 | void |
| 246 | vgahw_save_dac_state(u16 seg, struct saveDACcolors *info) |
| 247 | { |
| 248 | /* XXX: check this */ |
| 249 | SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE)); |
| 250 | SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS)); |
| 251 | SET_FARVAR(seg, info->pelmask, inb(VGAREG_PEL_MASK)); |
| 252 | vgahw_get_dac_regs(seg, info->dac, 0, 256); |
| 253 | SET_FARVAR(seg, info->color_select, 0); |
| 254 | } |
| 255 | |
| 256 | void |
| 257 | vgahw_restore_dac_state(u16 seg, struct saveDACcolors *info) |
| 258 | { |
| 259 | outb(GET_FARVAR(seg, info->pelmask), VGAREG_PEL_MASK); |
| 260 | vgahw_set_dac_regs(seg, info->dac, 0, 256); |
| 261 | outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS); |
| 262 | } |
| 263 | |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 264 | |
| 265 | /**************************************************************** |
| 266 | * Memory control |
| 267 | ****************************************************************/ |
| 268 | |
| 269 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 270 | vgahw_set_text_block_specifier(u8 spec) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 271 | { |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 272 | outw((spec << 8) | 0x03, VGAREG_SEQU_ADDRESS); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 273 | } |
| 274 | |
| 275 | void |
| 276 | get_font_access() |
| 277 | { |
| 278 | outw(0x0100, VGAREG_SEQU_ADDRESS); |
| 279 | outw(0x0402, VGAREG_SEQU_ADDRESS); |
| 280 | outw(0x0704, VGAREG_SEQU_ADDRESS); |
| 281 | outw(0x0300, VGAREG_SEQU_ADDRESS); |
| 282 | outw(0x0204, VGAREG_GRDC_ADDRESS); |
| 283 | outw(0x0005, VGAREG_GRDC_ADDRESS); |
| 284 | outw(0x0406, VGAREG_GRDC_ADDRESS); |
| 285 | } |
| 286 | |
| 287 | void |
| 288 | release_font_access() |
| 289 | { |
| 290 | outw(0x0100, VGAREG_SEQU_ADDRESS); |
| 291 | outw(0x0302, VGAREG_SEQU_ADDRESS); |
| 292 | outw(0x0304, VGAREG_SEQU_ADDRESS); |
| 293 | outw(0x0300, VGAREG_SEQU_ADDRESS); |
| 294 | u16 v = (inw(VGAREG_READ_MISC_OUTPUT) & 0x01) ? 0x0e : 0x0a; |
| 295 | outw((v << 8) | 0x06, VGAREG_GRDC_ADDRESS); |
| 296 | outw(0x0004, VGAREG_GRDC_ADDRESS); |
| 297 | outw(0x1005, VGAREG_GRDC_ADDRESS); |
| 298 | } |
| 299 | |
| 300 | |
| 301 | /**************************************************************** |
Kevin O'Connor | a0ecb05 | 2009-05-18 23:34:00 -0400 | [diff] [blame] | 302 | * CRTC registers |
| 303 | ****************************************************************/ |
| 304 | |
| 305 | static u16 |
| 306 | get_crtc() |
| 307 | { |
| 308 | return GET_BDA(crtc_address); |
| 309 | } |
| 310 | |
| 311 | void |
| 312 | vgahw_set_cursor_shape(u8 start, u8 end) |
| 313 | { |
| 314 | u16 crtc_addr = get_crtc(); |
| 315 | outb(0x0a, crtc_addr); |
| 316 | outb(start, crtc_addr + 1); |
| 317 | outb(0x0b, crtc_addr); |
| 318 | outb(end, crtc_addr + 1); |
| 319 | } |
| 320 | |
| 321 | void |
| 322 | vgahw_set_active_page(u16 address) |
| 323 | { |
| 324 | u16 crtc_addr = get_crtc(); |
| 325 | outb(0x0c, crtc_addr); |
| 326 | outb((address & 0xff00) >> 8, crtc_addr + 1); |
| 327 | outb(0x0d, crtc_addr); |
| 328 | outb(address & 0x00ff, crtc_addr + 1); |
| 329 | } |
| 330 | |
| 331 | void |
| 332 | vgahw_set_cursor_pos(u16 address) |
| 333 | { |
| 334 | u16 crtc_addr = get_crtc(); |
| 335 | outb(0x0e, crtc_addr); |
| 336 | outb((address & 0xff00) >> 8, crtc_addr + 1); |
| 337 | outb(0x0f, crtc_addr); |
| 338 | outb(address & 0x00ff, crtc_addr + 1); |
| 339 | } |
| 340 | |
| 341 | void |
| 342 | vgahw_set_scan_lines(u8 lines) |
| 343 | { |
| 344 | u16 crtc_addr = get_crtc(); |
| 345 | outb(0x09, crtc_addr); |
| 346 | u8 crtc_r9 = inb(crtc_addr + 1); |
| 347 | crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1); |
| 348 | outb(crtc_r9, crtc_addr + 1); |
| 349 | } |
| 350 | |
| 351 | // Get vertical display end |
| 352 | u16 |
| 353 | vgahw_get_vde() |
| 354 | { |
| 355 | u16 crtc_addr = get_crtc(); |
| 356 | outb(0x12, crtc_addr); |
| 357 | u16 vde = inb(crtc_addr + 1); |
| 358 | outb(0x07, crtc_addr); |
| 359 | u8 ovl = inb(crtc_addr + 1); |
| 360 | vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1); |
| 361 | return vde; |
| 362 | } |
| 363 | |
| 364 | |
| 365 | /**************************************************************** |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 366 | * Misc |
| 367 | ****************************************************************/ |
| 368 | |
| 369 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 370 | vgahw_enable_video_addressing(u8 disable) |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 371 | { |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 372 | u8 v = (disable & 1) ? 0x00 : 0x02; |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 373 | u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02; |
| 374 | outb(v | v2, VGAREG_WRITE_MISC_OUTPUT); |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 375 | } |
| 376 | |
| 377 | void |
Kevin O'Connor | 8bc059e | 2009-05-17 21:19:36 -0400 | [diff] [blame] | 378 | vgahw_init() |
Kevin O'Connor | c0c7df6 | 2009-05-17 18:11:33 -0400 | [diff] [blame] | 379 | { |
| 380 | // switch to color mode and enable CPU access 480 lines |
| 381 | outb(0xc3, VGAREG_WRITE_MISC_OUTPUT); |
| 382 | // more than 64k 3C4/04 |
| 383 | outb(0x04, VGAREG_SEQU_ADDRESS); |
| 384 | outb(0x02, VGAREG_SEQU_DATA); |
| 385 | } |
Kevin O'Connor | ca66864 | 2009-05-21 23:06:08 -0400 | [diff] [blame] | 386 | |
| 387 | void |
| 388 | vgahw_save_state(u16 seg, struct saveVideoHardware *info) |
| 389 | { |
| 390 | u16 crtc_addr = GET_BDA(crtc_address); |
| 391 | SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS)); |
| 392 | SET_FARVAR(seg, info->crtc_index, inb(crtc_addr)); |
| 393 | SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS)); |
| 394 | inb(VGAREG_ACTL_RESET); |
| 395 | u16 ar_index = inb(VGAREG_ACTL_ADDRESS); |
| 396 | SET_FARVAR(seg, info->actl_index, ar_index); |
| 397 | SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL)); |
| 398 | |
| 399 | u16 i; |
| 400 | for (i=0; i<4; i++) { |
| 401 | outb(i+1, VGAREG_SEQU_ADDRESS); |
| 402 | SET_FARVAR(seg, info->sequ_regs[i], inb(VGAREG_SEQU_DATA)); |
| 403 | } |
| 404 | outb(0, VGAREG_SEQU_ADDRESS); |
| 405 | SET_FARVAR(seg, info->sequ0, inb(VGAREG_SEQU_DATA)); |
| 406 | |
| 407 | for (i=0; i<25; i++) { |
| 408 | outb(i, crtc_addr); |
| 409 | SET_FARVAR(seg, info->crtc_regs[i], inb(crtc_addr + 1)); |
| 410 | } |
| 411 | |
| 412 | for (i=0; i<20; i++) { |
| 413 | inb(VGAREG_ACTL_RESET); |
| 414 | outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS); |
| 415 | SET_FARVAR(seg, info->actl_regs[i], inb(VGAREG_ACTL_READ_DATA)); |
| 416 | } |
| 417 | inb(VGAREG_ACTL_RESET); |
| 418 | |
| 419 | for (i=0; i<9; i++) { |
| 420 | outb(i, VGAREG_GRDC_ADDRESS); |
| 421 | SET_FARVAR(seg, info->grdc_regs[i], inb(VGAREG_GRDC_DATA)); |
| 422 | } |
| 423 | |
| 424 | SET_FARVAR(seg, info->crtc_addr, crtc_addr); |
| 425 | |
| 426 | /* XXX: read plane latches */ |
| 427 | for (i=0; i<4; i++) |
| 428 | SET_FARVAR(seg, info->plane_latch[i], 0); |
| 429 | } |
| 430 | |
| 431 | void |
| 432 | vgahw_restore_state(u16 seg, struct saveVideoHardware *info) |
| 433 | { |
| 434 | // Reset Attribute Ctl flip-flop |
| 435 | inb(VGAREG_ACTL_RESET); |
| 436 | |
| 437 | u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr); |
| 438 | |
| 439 | u16 i; |
| 440 | for (i=0; i<4; i++) { |
| 441 | outb(i+1, VGAREG_SEQU_ADDRESS); |
| 442 | outb(GET_FARVAR(seg, info->sequ_regs[i]), VGAREG_SEQU_DATA); |
| 443 | } |
| 444 | outb(0, VGAREG_SEQU_ADDRESS); |
| 445 | outb(GET_FARVAR(seg, info->sequ0), VGAREG_SEQU_DATA); |
| 446 | |
| 447 | // Disable CRTC write protection |
| 448 | outw(0x0011, crtc_addr); |
| 449 | // Set CRTC regs |
| 450 | for (i=0; i<25; i++) |
| 451 | if (i != 0x11) { |
| 452 | outb(i, crtc_addr); |
| 453 | outb(GET_FARVAR(seg, info->crtc_regs[i]), crtc_addr + 1); |
| 454 | } |
| 455 | // select crtc base address |
| 456 | u16 v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01; |
| 457 | if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS) |
| 458 | v |= 0x01; |
| 459 | outb(v, VGAREG_WRITE_MISC_OUTPUT); |
| 460 | |
| 461 | // enable write protection if needed |
| 462 | outb(0x11, crtc_addr); |
| 463 | outb(GET_FARVAR(seg, info->crtc_regs[0x11]), crtc_addr + 1); |
| 464 | |
| 465 | // Set Attribute Ctl |
| 466 | u16 ar_index = GET_FARVAR(seg, info->actl_index); |
| 467 | inb(VGAREG_ACTL_RESET); |
| 468 | for (i=0; i<20; i++) { |
| 469 | outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS); |
| 470 | outb(GET_FARVAR(seg, info->actl_regs[i]), VGAREG_ACTL_WRITE_DATA); |
| 471 | } |
| 472 | outb(ar_index, VGAREG_ACTL_ADDRESS); |
| 473 | inb(VGAREG_ACTL_RESET); |
| 474 | |
| 475 | for (i=0; i<9; i++) { |
| 476 | outb(i, VGAREG_GRDC_ADDRESS); |
| 477 | outb(GET_FARVAR(seg, info->grdc_regs[i]), VGAREG_GRDC_DATA); |
| 478 | } |
| 479 | |
| 480 | outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS); |
| 481 | outb(GET_FARVAR(seg, info->crtc_index), crtc_addr); |
| 482 | outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS); |
| 483 | outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa); |
| 484 | } |