Kevin O'Connor | 3471fdb | 2012-01-14 19:02:43 -0500 | [diff] [blame] | 1 | // Standard VGA IO port access |
| 2 | // |
| 3 | // Copyright (C) 2012 Kevin O'Connor <kevin@koconnor.net> |
| 4 | // |
| 5 | // This file may be distributed under the terms of the GNU LGPLv3 license. |
| 6 | |
Kevin O'Connor | f98bbf0 | 2012-01-27 23:09:02 -0500 | [diff] [blame] | 7 | #include "farptr.h" // GET_FARVAR |
Kevin O'Connor | c682ffe | 2016-08-05 11:48:20 -0400 | [diff] [blame] | 8 | #include "stdvga.h" // VGAREG_PEL_MASK |
| 9 | #include "vgautil.h" // stdvga_pelmask_read |
Kevin O'Connor | 4ade523 | 2013-09-18 21:41:48 -0400 | [diff] [blame] | 10 | #include "x86.h" // inb |
Kevin O'Connor | 3471fdb | 2012-01-14 19:02:43 -0500 | [diff] [blame] | 11 | |
| 12 | u8 |
| 13 | stdvga_pelmask_read(void) |
| 14 | { |
| 15 | return inb(VGAREG_PEL_MASK); |
| 16 | } |
| 17 | |
| 18 | void |
| 19 | stdvga_pelmask_write(u8 value) |
| 20 | { |
| 21 | outb(value, VGAREG_PEL_MASK); |
| 22 | } |
| 23 | |
| 24 | |
| 25 | u8 |
| 26 | stdvga_misc_read(void) |
| 27 | { |
| 28 | return inb(VGAREG_READ_MISC_OUTPUT); |
| 29 | } |
| 30 | |
| 31 | void |
| 32 | stdvga_misc_write(u8 value) |
| 33 | { |
| 34 | outb(value, VGAREG_WRITE_MISC_OUTPUT); |
| 35 | } |
| 36 | |
| 37 | void |
| 38 | stdvga_misc_mask(u8 off, u8 on) |
| 39 | { |
| 40 | stdvga_misc_write((stdvga_misc_read() & ~off) | on); |
| 41 | } |
| 42 | |
| 43 | |
| 44 | u8 |
| 45 | stdvga_sequ_read(u8 index) |
| 46 | { |
| 47 | outb(index, VGAREG_SEQU_ADDRESS); |
| 48 | return inb(VGAREG_SEQU_DATA); |
| 49 | } |
| 50 | |
| 51 | void |
| 52 | stdvga_sequ_write(u8 index, u8 value) |
| 53 | { |
| 54 | outw((value<<8) | index, VGAREG_SEQU_ADDRESS); |
| 55 | } |
| 56 | |
| 57 | void |
| 58 | stdvga_sequ_mask(u8 index, u8 off, u8 on) |
| 59 | { |
| 60 | outb(index, VGAREG_SEQU_ADDRESS); |
| 61 | u8 v = inb(VGAREG_SEQU_DATA); |
| 62 | outb((v & ~off) | on, VGAREG_SEQU_DATA); |
| 63 | } |
| 64 | |
| 65 | |
| 66 | u8 |
| 67 | stdvga_grdc_read(u8 index) |
| 68 | { |
| 69 | outb(index, VGAREG_GRDC_ADDRESS); |
| 70 | return inb(VGAREG_GRDC_DATA); |
| 71 | } |
| 72 | |
| 73 | void |
| 74 | stdvga_grdc_write(u8 index, u8 value) |
| 75 | { |
| 76 | outw((value<<8) | index, VGAREG_GRDC_ADDRESS); |
| 77 | } |
| 78 | |
| 79 | void |
| 80 | stdvga_grdc_mask(u8 index, u8 off, u8 on) |
| 81 | { |
| 82 | outb(index, VGAREG_GRDC_ADDRESS); |
| 83 | u8 v = inb(VGAREG_GRDC_DATA); |
| 84 | outb((v & ~off) | on, VGAREG_GRDC_DATA); |
| 85 | } |
| 86 | |
| 87 | |
| 88 | u8 |
| 89 | stdvga_crtc_read(u16 crtc_addr, u8 index) |
| 90 | { |
| 91 | outb(index, crtc_addr); |
| 92 | return inb(crtc_addr + 1); |
| 93 | } |
| 94 | |
| 95 | void |
| 96 | stdvga_crtc_write(u16 crtc_addr, u8 index, u8 value) |
| 97 | { |
| 98 | outw((value<<8) | index, crtc_addr); |
| 99 | } |
| 100 | |
| 101 | void |
| 102 | stdvga_crtc_mask(u16 crtc_addr, u8 index, u8 off, u8 on) |
| 103 | { |
| 104 | outb(index, crtc_addr); |
| 105 | u8 v = inb(crtc_addr + 1); |
| 106 | outb((v & ~off) | on, crtc_addr + 1); |
| 107 | } |
| 108 | |
| 109 | |
| 110 | u8 |
| 111 | stdvga_attr_read(u8 index) |
| 112 | { |
| 113 | inb(VGAREG_ACTL_RESET); |
| 114 | u8 orig = inb(VGAREG_ACTL_ADDRESS); |
| 115 | outb(index, VGAREG_ACTL_ADDRESS); |
| 116 | u8 v = inb(VGAREG_ACTL_READ_DATA); |
| 117 | inb(VGAREG_ACTL_RESET); |
| 118 | outb(orig, VGAREG_ACTL_ADDRESS); |
| 119 | return v; |
| 120 | } |
| 121 | |
| 122 | void |
| 123 | stdvga_attr_write(u8 index, u8 value) |
| 124 | { |
| 125 | inb(VGAREG_ACTL_RESET); |
| 126 | u8 orig = inb(VGAREG_ACTL_ADDRESS); |
| 127 | outb(index, VGAREG_ACTL_ADDRESS); |
| 128 | outb(value, VGAREG_ACTL_WRITE_DATA); |
| 129 | outb(orig, VGAREG_ACTL_ADDRESS); |
| 130 | } |
| 131 | |
| 132 | void |
| 133 | stdvga_attr_mask(u8 index, u8 off, u8 on) |
| 134 | { |
| 135 | inb(VGAREG_ACTL_RESET); |
| 136 | u8 orig = inb(VGAREG_ACTL_ADDRESS); |
| 137 | outb(index, VGAREG_ACTL_ADDRESS); |
| 138 | u8 v = inb(VGAREG_ACTL_READ_DATA); |
| 139 | outb((v & ~off) | on, VGAREG_ACTL_WRITE_DATA); |
| 140 | outb(orig, VGAREG_ACTL_ADDRESS); |
| 141 | } |
| 142 | |
| 143 | u8 |
| 144 | stdvga_attrindex_read(void) |
| 145 | { |
| 146 | inb(VGAREG_ACTL_RESET); |
| 147 | return inb(VGAREG_ACTL_ADDRESS); |
| 148 | } |
| 149 | |
| 150 | void |
| 151 | stdvga_attrindex_write(u8 value) |
| 152 | { |
| 153 | inb(VGAREG_ACTL_RESET); |
| 154 | outb(value, VGAREG_ACTL_ADDRESS); |
| 155 | } |
| 156 | |
| 157 | |
| 158 | void |
| 159 | stdvga_dac_read(u16 seg, u8 *data_far, u8 start, int count) |
| 160 | { |
| 161 | outb(start, VGAREG_DAC_READ_ADDRESS); |
| 162 | while (count) { |
| 163 | SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); |
| 164 | data_far++; |
| 165 | SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); |
| 166 | data_far++; |
| 167 | SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA)); |
| 168 | data_far++; |
| 169 | count--; |
| 170 | } |
| 171 | } |
| 172 | |
| 173 | void |
| 174 | stdvga_dac_write(u16 seg, u8 *data_far, u8 start, int count) |
| 175 | { |
| 176 | outb(start, VGAREG_DAC_WRITE_ADDRESS); |
| 177 | while (count) { |
| 178 | outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); |
| 179 | data_far++; |
| 180 | outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); |
| 181 | data_far++; |
| 182 | outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA); |
| 183 | data_far++; |
| 184 | count--; |
| 185 | } |
| 186 | } |