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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Stefan Taunerb4e06bd2012-08-20 00:24:22 +000028#include <stdlib.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000029#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000030#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000031#include "hwaccess.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000032
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000033#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000035 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000036 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000037/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000038void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000039{
Andriy Gapon65c1b862008-05-22 13:22:45 +000040 OUTB(0x87, port);
41 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000042}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000043
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000044/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000045void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000046{
Andriy Gapon65c1b862008-05-22 13:22:45 +000047 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000048}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000049
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000050/* Generic Super I/O helper functions */
51uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000052{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000053 OUTB(reg, port);
54 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000055}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000056
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000057void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000058{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000059 OUTB(reg, port);
60 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000061}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000062
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000063void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000064{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000065 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000066
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000067 OUTB(reg, port);
68 tmp = INB(port + 1) & ~mask;
69 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000070}
71
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +000072/* Winbond W83697 documentation indicates that the index register has to be written for each access. */
73void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
74{
75 uint8_t tmp;
76
77 OUTB(reg, port);
78 tmp = INB(port + 1) & ~mask;
79 OUTB(reg, port);
80 OUTB(tmp | (data & mask), port + 1);
81}
82
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000083/* Not used yet. */
84#if 0
85static int enable_flash_decode_superio(void)
86{
87 int ret;
88 uint8_t tmp;
89
90 switch (superio.vendor) {
91 case SUPERIO_VENDOR_NONE:
92 ret = -1;
93 break;
94 case SUPERIO_VENDOR_ITE:
95 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000096 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000097 tmp = sio_read(superio.port, 0x24);
98 tmp |= 0xfc;
99 sio_write(superio.port, 0x24, tmp);
100 exit_conf_mode_ite(superio.port);
101 ret = 0;
102 break;
103 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000104 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000105 ret = -1;
106 break;
107 }
108 return ret;
109}
110#endif
111
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000112/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000113 * SMSC FDC37B787: Raise GPIO50
114 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000115static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000116{
117 uint8_t id, val;
118
119 OUTB(0x55, port); /* enter conf mode */
120 id = sio_read(port, 0x20);
121 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000122 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000123 OUTB(0xAA, port); /* leave conf mode */
124 return -1;
125 }
126
127 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
128
129 val = sio_read(port, 0xC8); /* GP50 */
130 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
131 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000132 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000133 OUTB(0xAA, port);
134 return -1;
135 }
136
137 sio_mask(port, 0xF9, 0x01, 0x01);
138
139 OUTB(0xAA, port); /* Leave conf mode */
140 return 0;
141}
142
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000143/*
144 * Suited for:
145 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000146 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000147static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000148{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000149 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000150}
151
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000152struct winbond_mux {
153 uint8_t reg; /* 0 if the corresponding pin is not muxed */
154 uint8_t data; /* reg/data/mask may be directly ... */
155 uint8_t mask; /* ... passed to sio_mask */
156};
157
158struct winbond_port {
159 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
160 uint8_t ldn; /* LDN this GPIO register is located in */
161 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
162 the GPIO port */
163 uint8_t base; /* base register in that LDN for the port */
164};
165
166struct winbond_chip {
167 uint8_t device_id; /* reg 0x20 of the expected w83626x */
168 uint8_t gpio_port_count;
169 const struct winbond_port *port;
170};
171
172
173#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
174
175enum winbond_id {
176 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000177 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000178 WINBOND_W83627THF_ID = 0x82,
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000179 WINBOND_W83697HF_ID = 0x60,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000180};
181
182static const struct winbond_mux w83627hf_port2_mux[8] = {
183 {0x2A, 0x01, 0x01}, /* or MIDI */
184 {0x2B, 0x80, 0x80}, /* or SPI */
185 {0x2B, 0x40, 0x40}, /* or SPI */
186 {0x2B, 0x20, 0x20}, /* or power LED */
187 {0x2B, 0x10, 0x10}, /* or watchdog */
188 {0x2B, 0x08, 0x08}, /* or infra red */
189 {0x2B, 0x04, 0x04}, /* or infra red */
190 {0x2B, 0x03, 0x03} /* or IRQ1 input */
191};
192
193static const struct winbond_port w83627hf[3] = {
194 UNIMPLEMENTED_PORT,
195 {w83627hf_port2_mux, 0x08, 0, 0xF0},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000196 UNIMPLEMENTED_PORT,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000197};
198
Michael Karcherea36c9c2010-06-27 15:07:52 +0000199static const struct winbond_mux w83627ehf_port2_mux[8] = {
200 {0x29, 0x06, 0x02}, /* or MIDI */
201 {0x29, 0x06, 0x02},
202 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
203 {0x24, 0x02, 0x00},
204 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
205 {0x2A, 0x01, 0x01},
206 {0x2A, 0x01, 0x01},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000207 {0x2A, 0x01, 0x01},
Michael Karcherea36c9c2010-06-27 15:07:52 +0000208};
209
210static const struct winbond_port w83627ehf[6] = {
211 UNIMPLEMENTED_PORT,
212 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
213 UNIMPLEMENTED_PORT,
214 UNIMPLEMENTED_PORT,
215 UNIMPLEMENTED_PORT,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000216 UNIMPLEMENTED_PORT,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000217};
218
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000219static const struct winbond_mux w83627thf_port4_mux[8] = {
220 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
221 {0x2D, 0x02, 0x02}, /* or resume reset */
222 {0x2D, 0x04, 0x04}, /* or S3 input */
223 {0x2D, 0x08, 0x08}, /* or PSON# */
224 {0x2D, 0x10, 0x10}, /* or PWROK */
225 {0x2D, 0x20, 0x20}, /* or suspend LED */
226 {0x2D, 0x40, 0x40}, /* or panel switch input */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000227 {0x2D, 0x80, 0x80}, /* or panel switch output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000228};
229
230static const struct winbond_port w83627thf[5] = {
231 UNIMPLEMENTED_PORT, /* GPIO1 */
232 UNIMPLEMENTED_PORT, /* GPIO2 */
233 UNIMPLEMENTED_PORT, /* GPIO3 */
234 {w83627thf_port4_mux, 0x09, 1, 0xF4},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000235 UNIMPLEMENTED_PORT, /* GPIO5 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000236};
237
238static const struct winbond_chip winbond_chips[] = {
239 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000240 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000241 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
242};
243
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000244#define WINBOND_SUPERIO_PORT1 0x2e
245#define WINBOND_SUPERIO_PORT2 0x4e
246
247/* We don't really care about the hardware monitor, but it offers better (more specific) device ID info than
248 * the simple device ID in the normal configuration registers.
249 * Note: This function expects to be called while the Super I/O is in config mode.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000250 */
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000251static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000252{
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000253 uint16_t hwmport;
254 uint16_t hwm_vendorid;
255 uint8_t hwm_deviceid;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000256
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000257 sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
258 if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) {
259 msg_pinfo("W836xx hardware monitor disabled or does not exist.\n");
260 return 0;
261 }
262 /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
263 hwmport = sio_read(sio_port, 0x60) << 8;
264 hwmport |= sio_read(sio_port, 0x61);
265 /* HWM address register = HWM base address + 5. */
266 hwmport += 5;
267 msg_pdbg2("W836xx Hardware Monitor at port %04x\n", hwmport);
268 /* FIXME: This busy check should happen before each HWM access. */
269 if (INB(hwmport) & 0x80) {
270 msg_pinfo("W836xx hardware monitor busy, ignoring it.\n");
271 return 0;
272 }
273 /* Set HBACS=1. */
274 sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80);
275 /* Read upper byte of vendor ID. */
276 hwm_vendorid = sio_read(hwmport, 0x4f) << 8;
277 /* Set HBACS=0. */
278 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80);
279 /* Read lower byte of vendor ID. */
280 hwm_vendorid |= sio_read(hwmport, 0x4f);
281 if (hwm_vendorid != 0x5ca3) {
282 msg_pinfo("W836xx hardware monitor vendor ID weirdness: expected 0x5ca3, got %04x\n",
283 hwm_vendorid);
284 return 0;
285 }
286 /* Set Bank=0. */
287 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07);
288 /* Read "chip" ID. We call this one the device ID. */
289 hwm_deviceid = sio_read(hwmport, 0x58);
290 return hwm_deviceid;
291}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000292
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000293void probe_superio_winbond(void)
294{
295 struct superio s = {};
296 uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
297 uint16_t *i = winbond_ports;
298 uint8_t model;
299 uint8_t tmp;
300
301 s.vendor = SUPERIO_VENDOR_WINBOND;
302 for (; *i; i++) {
303 s.port = *i;
304 /* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */
305 w836xx_ext_enter(s.port);
306 model = sio_read(s.port, 0x20);
307 /* No response, no point leaving the config mode. */
308 if (model == 0xff)
309 continue;
310 /* Try to leave config mode. If the ID register is still readable, it's not a Winbond chip. */
311 w836xx_ext_leave(s.port);
312 if (model == sio_read(s.port, 0x20)) {
313 msg_pdbg("W836xx enter config mode worked or we were already in config mode. W836xx "
314 "leave config mode had no effect.\n");
315 if (model == 0x87) {
316 /* ITE IT8707F and IT8710F are special: They need the W837xx enter sequence,
317 * but they want the ITE exit sequence. Handle them here.
318 */
319 tmp = sio_read(s.port, 0x21);
320 switch (tmp) {
321 case 0x07:
322 case 0x10:
323 s.vendor = SUPERIO_VENDOR_ITE;
324 s.model = (0x87 << 8) | tmp ;
325 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
326 "0x%x\n", s.model, s.port);
327 register_superio(s);
328 /* Exit ITE config mode. */
329 exit_conf_mode_ite(s.port);
330 /* Restore vendor for next loop iteration. */
331 s.vendor = SUPERIO_VENDOR_WINBOND;
332 continue;
333 }
334 }
335 msg_pinfo("Active config mode, unknown reg 0x20 ID: %02x.\n", model);
336 msg_pinfo("Please send the output of \"flashrom -V\" to \n"
337 "flashrom@flashrom.org with W836xx: your board name: flashrom -V\n"
338 "as the subject to help us finish support for your Super I/O. Thanks.\n");
339 continue;
340 }
341 /* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */
342 w836xx_ext_enter(s.port);
343 s.model = sio_read(s.port, 0x20);
344 switch (s.model) {
345 case WINBOND_W83627HF_ID:
346 case WINBOND_W83627EHF_ID:
347 case WINBOND_W83627THF_ID:
348 msg_pdbg("Found Winbond Super I/O, id %02hx\n", s.model);
349 register_superio(s);
350 break;
351 case WINBOND_W83697HF_ID:
352 /* This code is extremely paranoid. */
353 tmp = sio_read(s.port, 0x26) & 0x40;
354 if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
355 ((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
356 msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
357 "%02x at port %04x\n", s.model, s.port);
358 break;
359 }
360 tmp = w836xx_deviceid_hwmon(s.port);
361 /* FIXME: This might be too paranoid... */
362 if (!tmp) {
363 msg_pdbg("Probably not a Winbond Super I/O\n");
364 break;
365 }
366 if (tmp != s.model) {
367 msg_pinfo("W83 series hardware monitor device ID weirdness: expected %02x, "
368 "got %02x\n", WINBOND_W83697HF_ID, tmp);
369 break;
370 }
371 msg_pinfo("Found Winbond Super I/O, id %02hx\n", s.model);
372 register_superio(s);
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000373 break;
374 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000375 w836xx_ext_leave(s.port);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000376 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000377 return;
378}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000379
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000380static const struct winbond_chip *winbond_superio_chipdef(void)
381{
382 int i, j;
383
384 for (i = 0; i < superio_count; i++) {
385 if (superios[i].vendor != SUPERIO_VENDOR_WINBOND)
386 continue;
387 for (j = 0; j < ARRAY_SIZE(winbond_chips); j++)
388 if (winbond_chips[j].device_id == superios[i].model)
389 return &winbond_chips[j];
390 }
391 return NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000392}
393
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000394/*
395 * The chipid parameter goes away as soon as we have Super I/O matching in the
396 * board enable table. The call to winbond_superio_detect() goes away as
397 * soon as we have generic Super I/O detection code.
398 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000399static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
400 int pin, int raise)
401{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000402 const struct winbond_chip *chip = NULL;
403 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000404 int port = pin / 10;
405 int bit = pin % 10;
406
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000407 chip = winbond_superio_chipdef();
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000408 if (!chip) {
409 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
410 return -1;
411 }
Michael Karcher979d9252010-06-29 14:44:40 +0000412 if (chip->device_id != chipid) {
413 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
414 "expected %x\n", chip->device_id, chipid);
415 return -1;
416 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000417 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
418 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
419 pin);
420 return -1;
421 }
422
423 gpio = &chip->port[port - 1];
424
425 if (gpio->ldn == 0) {
426 msg_perr("\nERROR: GPIO%d is not supported yet on this"
427 " winbond chip\n", port);
428 return -1;
429 }
430
431 w836xx_ext_enter(base);
432
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000433 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000434 sio_write(base, 0x07, gpio->ldn);
435
436 /* Activate logical device. */
437 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
438
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000439 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000440 if (gpio->mux && gpio->mux[bit].reg)
441 sio_mask(base, gpio->mux[bit].reg,
442 gpio->mux[bit].data, gpio->mux[bit].mask);
443
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000444 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000445 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
446 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
447
448 w836xx_ext_leave(base);
449
450 return 0;
451}
452
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000453/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000454 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000455 *
456 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000457 * - Agami Aruma
458 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000459 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000460static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000461{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000462 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000463}
464
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000465/*
Joshua Roysf280a382010-08-07 21:49:11 +0000466 * Winbond W83627HF: Raise GPIO25.
467 *
468 * Suited for:
469 * - MSI MS-6577
470 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000471static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000472{
473 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
474}
475
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000476/*
Stefan Taunerff80e682011-07-20 16:34:18 +0000477 * Winbond W83627EHF: Raise GPIO22.
Michael Karcherea36c9c2010-06-27 15:07:52 +0000478 *
479 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000480 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000481 */
Stefan Taunerff80e682011-07-20 16:34:18 +0000482static int w83627ehf_gpio22_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000483{
Stefan Taunerff80e682011-07-20 16:34:18 +0000484 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
Michael Karcherea36c9c2010-06-27 15:07:52 +0000485}
486
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000487/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000488 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000489 *
490 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000491 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000492 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000493static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000494{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000495 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000496}
497
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000498/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000499 * Winbond W83627THF: Raise GPIO 44.
500 *
501 * Suited for:
502 * - MSI K8N Neo3
503 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000504static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000505{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000506 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000507}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000508
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000509/*
David Borgb6417a62010-08-02 08:29:34 +0000510 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000511 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000512 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000513static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000514{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000515 w836xx_ext_enter(port);
516 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000517 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000518 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000519 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000520 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000521}
522
David Borgb02c62b2012-05-05 20:43:42 +0000523/**
524 * Enable MEMW# and set ROM size to max.
525 * Supported chips:
526 * W83697HF/F/HG, W83697SF/UF/UG
527 */
528void w83697xx_memw_enable(uint16_t port)
529{
530 w836xx_ext_enter(port);
531 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
532 if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
533
534 /* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
535 /* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
536 /* These bits are reserved on W83697HF/F/HG */
537 /* Shouldn't be needed though. */
538
539 /* CR28 Bit3 must be set to 1 to enable flash access to */
540 /* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
541 /* This bit is reserved on W83697HF/F/HG which default to 0 */
542 sio_mask(port, 0x28, 0x08, 0x08);
543
544 /* Enable MEMW# and set ROM size select to max. (4M)*/
545 sio_mask(port, 0x24, 0x28, 0x38);
546
547 } else {
548 msg_perr("WARNING: Flash interface in use by GPIO!\n");
549 }
550 } else {
551 msg_pinfo("BIOS ROM is disabled\n");
552 }
553 w836xx_ext_leave(port);
554}
555
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000556/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000557 * Suited for:
Stefan Taunerb6304c12012-08-09 23:25:27 +0000558 * - Biostar M7VIQ: VIA KM266 + VT8235
559 */
560static int w83697xx_memw_enable_2e(void)
561{
562 w83697xx_memw_enable(0x2E);
563
564 return 0;
565}
566
567
568/*
569 * Suited for:
Tadas Slotkus3dcdc032012-08-25 03:53:12 +0000570 * - DFI AD77: VIA KT400 + VT8235 + W83697HF
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000571 * - EPoX EP-8K5A2: VIA KT333 + VT8235
572 * - Albatron PM266A Pro: VIA P4M266A + VT8235
573 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
574 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
575 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000576 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Mattias Mattssone8388242010-09-11 15:25:48 +0000577 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
Sergey A Lichackf3a4bff2010-09-07 18:14:53 +0000578 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
Uwe Hermann17da61e2010-10-05 21:48:43 +0000579 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
Pawel Rozanski1d233072011-06-19 16:52:48 +0000580 * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000581 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000582static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000583{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000584 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000585
Luc Verhaegen73d21192009-12-23 00:54:26 +0000586 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000587}
588
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000589/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000590 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000591 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000592 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000593static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000594{
595 w836xx_memw_enable(0x4E);
596
597 return 0;
598}
599
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000600/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000601 * Suited for all boards with ITE IT8705F.
602 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000603 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000604int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000605{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000606 uint8_t tmp;
607 int ret = 0;
608
Luc Verhaegen21f54962010-01-20 14:45:07 +0000609 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000610 tmp = sio_read(port, 0x24);
611 /* Check if at least one flash segment is enabled. */
612 if (tmp & 0xf0) {
613 /* The IT8705F will respond to LPC cycles and translate them. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000614 internal_buses_supported = BUS_PARALLEL;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000615 /* Flash ROM I/F Writes Enable */
616 tmp |= 0x04;
617 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
618 if (tmp & 0x02) {
619 /* The data sheet contradicts itself about max size. */
620 max_rom_decode.parallel = 1024 * 1024;
621 msg_pinfo("IT8705F with very unusual settings. Please "
622 "send the output of \"flashrom -V\" to \n"
Paul Menzelab6328f2010-10-08 11:03:02 +0000623 "flashrom@flashrom.org with "
624 "IT8705: your board name: flashrom -V\n"
625 "as the subject to help us finish "
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000626 "support for your Super I/O. Thanks.\n");
627 ret = 1;
628 } else if (tmp & 0x08) {
629 max_rom_decode.parallel = 512 * 1024;
630 } else {
631 max_rom_decode.parallel = 256 * 1024;
632 }
633 /* Safety checks. The data sheet is unclear here: Segments 1+3
634 * overlap, no segment seems to cover top - 1MB to top - 512kB.
635 * We assume that certain combinations make no sense.
636 */
637 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
638 (!(tmp & 0x10)) || /* 128 kB dis */
639 (!(tmp & 0x40))) { /* 256/512 kB dis */
640 msg_perr("Inconsistent IT8705F decode size!\n");
641 ret = 1;
642 }
643 if (sio_read(port, 0x25) != 0) {
644 msg_perr("IT8705F flash data pins disabled!\n");
645 ret = 1;
646 }
647 if (sio_read(port, 0x26) != 0) {
648 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
649 ret = 1;
650 }
651 if (sio_read(port, 0x27) != 0) {
652 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
653 ret = 1;
654 }
655 if ((sio_read(port, 0x29) & 0x10) != 0) {
656 msg_perr("IT8705F flash write enable pin disabled!\n");
657 ret = 1;
658 }
659 if ((sio_read(port, 0x29) & 0x08) != 0) {
660 msg_perr("IT8705F flash chip select pin disabled!\n");
661 ret = 1;
662 }
663 if ((sio_read(port, 0x29) & 0x04) != 0) {
664 msg_perr("IT8705F flash read strobe pin disabled!\n");
665 ret = 1;
666 }
667 if ((sio_read(port, 0x29) & 0x03) != 0) {
668 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
669 /* Not really an error if you use flash chips smaller
670 * than 256 kByte, but such a configuration is unlikely.
671 */
672 ret = 1;
673 }
674 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
675 max_rom_decode.parallel);
676 if (ret) {
677 msg_pinfo("Not enabling IT8705F flash write.\n");
678 } else {
679 sio_write(port, 0x24, tmp);
680 }
681 } else {
682 msg_pdbg("No IT8705F flash segment enabled.\n");
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000683 ret = 0;
684 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000685 exit_conf_mode_ite(port);
686
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000687 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000688}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000689
Mattias Mattssonfb60cec2010-09-13 19:39:25 +0000690/*
691 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
692 * It uses the Winbond command sequence to enter extended configuration
693 * mode and the ITE sequence to exit.
694 *
695 * Registers seems similar to the ones on ITE IT8710F.
696 */
697static int it8707f_write_enable(uint8_t port)
698{
699 uint8_t tmp;
700
701 w836xx_ext_enter(port);
702
703 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
704 tmp = sio_read(port, 0x23);
705 tmp |= (1 << 3);
706 sio_write(port, 0x23, tmp);
707
708 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
709 tmp = sio_read(port, 0x24);
710 tmp |= (1 << 2) | (1 << 3);
711 sio_write(port, 0x24, tmp);
712
713 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
714 tmp = sio_read(port, 0x23);
715 tmp &= ~(1 << 3);
716 sio_write(port, 0x23, tmp);
717
718 exit_conf_mode_ite(port);
719
720 return 0;
721}
722
723/*
724 * Suited for:
725 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
726 */
727static int it8707f_write_enable_2e(void)
728{
729 return it8707f_write_enable(0x2e);
730}
731
Michael Karchercba52de2011-03-06 12:07:19 +0000732#define PC87360_ID 0xE1
733#define PC87364_ID 0xE4
734
735static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000736{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000737 static const int bankbase[] = {0, 4, 8, 10, 12};
738 int gpio_bank = gpio / 8;
739 int gpio_pin = gpio % 8;
740 uint16_t baseport;
741 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000742
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000743 if (gpio_bank > 4) {
Michael Karchercba52de2011-03-06 12:07:19 +0000744 msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000745 return -1;
746 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000747
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000748 id = sio_read(0x2E, 0x20);
Michael Karchercba52de2011-03-06 12:07:19 +0000749 if (id != chipid) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000750 msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
751 id, chipid);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000752 return -1;
753 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000754
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000755 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
756 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
757 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
758 msg_perr("PC87360: invalid GPIO base address %04x\n",
759 baseport);
760 return -1;
761 }
762 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
763 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
764 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000765
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000766 val = INB(baseport + bankbase[gpio_bank]);
767 if (raise)
768 val |= 1 << gpio_pin;
769 else
770 val &= ~(1 << gpio_pin);
771 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000772
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000773 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000774}
775
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000776/*
777 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000778 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000779static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000780{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000781 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000782 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000783 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000784
Luc Verhaegen73d21192009-12-23 00:54:26 +0000785 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
786 switch (dev->device_id) {
787 case 0x3177: /* VT8235 */
Helge Wagnerdd73d832012-08-24 23:03:46 +0000788 case 0x3227: /* VT8237/VT8237R */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000789 case 0x3337: /* VT8237A */
790 break;
791 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000792 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000793 return -1;
794 }
795
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000796 if ((gpio >= 12) && (gpio <= 15)) {
797 /* GPIO12-15 -> output */
798 val = pci_read_byte(dev, 0xE4);
799 val |= 0x10;
800 pci_write_byte(dev, 0xE4, val);
801 } else if (gpio == 9) {
802 /* GPIO9 -> Output */
803 val = pci_read_byte(dev, 0xE4);
804 val |= 0x20;
805 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000806 } else if (gpio == 5) {
807 val = pci_read_byte(dev, 0xE4);
808 val |= 0x01;
809 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000810 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000811 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000812 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000813 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000814 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000815
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000816 /* We need the I/O Base Address for this board's flash enable. */
817 base = pci_read_word(dev, 0x88) & 0xff80;
818
David Bartleyf58d3642009-12-09 07:53:01 +0000819 offset = 0x4C + gpio / 8;
820 bit = 0x01 << (gpio % 8);
821
822 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000823 if (raise)
824 val |= bit;
825 else
826 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000827 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000828
Uwe Hermanna7e05482007-05-09 10:17:44 +0000829 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000830}
831
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000832/*
833 * Suited for:
834 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000835 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000836static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000837{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000838 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
839 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000840}
841
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000842/*
843 * Suited for:
844 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000845 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000846static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000847{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000848 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000849}
850
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000851/*
852 * Suited for:
853 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000854 *
855 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
856 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000857 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000858static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000859{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000860 return via_vt823x_gpio_set(15, 1);
861}
862
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000863/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000864 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
865 *
866 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000867 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
868 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000869 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000870static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000871{
872 int ret;
873
874 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000875 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000876
Luc Verhaegen73d21192009-12-23 00:54:26 +0000877 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000878}
879
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000880/*
881 * Suited for:
882 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000883 *
884 * This is rather nasty code, but there's no way to do this cleanly.
885 * We're basically talking to some unknown device on SMBus, my guess
886 * is that it is the Winbond W83781D that lives near the DIP BIOS.
887 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000888static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000889{
890 uint8_t tmp;
891 int i;
892
893#define ASUSP5A_LOOP 5000
894
Andriy Gapon65c1b862008-05-22 13:22:45 +0000895 OUTB(0x00, 0xE807);
896 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000897
Andriy Gapon65c1b862008-05-22 13:22:45 +0000898 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000899
900 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000901 OUTB(0xE1, 0xFF);
902 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000903 break;
904 }
905
906 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000907 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000908 return -1;
909 }
910
Andriy Gapon65c1b862008-05-22 13:22:45 +0000911 OUTB(0x20, 0xE801);
912 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000913
Andriy Gapon65c1b862008-05-22 13:22:45 +0000914 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000915
916 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000917 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000918 if (tmp & 0x70)
919 break;
920 }
921
922 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000923 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000924 return -1;
925 }
926
Andriy Gapon65c1b862008-05-22 13:22:45 +0000927 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000928 tmp &= ~0x02;
929
Andriy Gapon65c1b862008-05-22 13:22:45 +0000930 OUTB(0x00, 0xE807);
931 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000932
Andriy Gapon65c1b862008-05-22 13:22:45 +0000933 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000934
Andriy Gapon65c1b862008-05-22 13:22:45 +0000935 OUTB(0xFF, 0xE800);
936 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000937
Andriy Gapon65c1b862008-05-22 13:22:45 +0000938 OUTB(0x20, 0xE801);
939 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000940
Andriy Gapon65c1b862008-05-22 13:22:45 +0000941 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000942
943 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000944 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000945 if (tmp & 0x70)
946 break;
947 }
948
949 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000950 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000951 return -1;
952 }
953
954 return 0;
955}
956
Luc Verhaegena7e30502009-12-09 11:39:02 +0000957/*
958 * Set GPIO lines in the Broadcom HT-1000 southbridge.
959 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000960 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +0000961 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000962static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +0000963{
964 /* GPIO 0 reg from PM regs */
965 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
966 sio_mask(0xcd6, 0x44, 0x24, 0x24);
967
968 return 0;
969}
970
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000971/*
972 * Set GPIO lines in the Broadcom HT-1000 southbridge.
973 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000974 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000975 */
976static int board_hp_dl165_g6_enable(void)
977{
978 /* Variant of DL145, with slightly different pin placement. */
979 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
980 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
981
982 return 0;
983}
984
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000985static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000986{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000987 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000988 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000989
990 return 0;
991}
992
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000993/*
994 * Suited for:
995 * - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000996 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000997static int board_shuttle_fn25(void)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000998{
999 struct pci_dev *dev;
1000
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001001 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA bridge. */
Luc Verhaegen20fdce12009-10-21 12:05:50 +00001002 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001003 msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
Luc Verhaegen20fdce12009-10-21 12:05:50 +00001004 return -1;
1005 }
1006
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001007 /* One of those bits seems to be connected to TBL#, but -ENOINFO. */
Luc Verhaegen20fdce12009-10-21 12:05:50 +00001008 pci_write_byte(dev, 0x92, 0);
1009
1010 return 0;
1011}
1012
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001013/*
Mattias Mattssonf4925162010-09-16 22:09:18 +00001014 * Suited for:
1015 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
1016 */
Mattias Mattssonf4925162010-09-16 22:09:18 +00001017static int board_ecs_geforce6100sm_m(void)
1018{
1019 struct pci_dev *dev;
1020 uint32_t tmp;
1021
1022 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
1023 if (!dev) {
1024 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
1025 return -1;
1026 }
1027
1028 tmp = pci_read_byte(dev, 0xE0);
1029 tmp &= ~(1 << 3);
1030 pci_write_byte(dev, 0xE0, tmp);
1031
1032 return 0;
1033}
1034
1035/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001036 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001037 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001038static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001039{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001040 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001041 uint16_t base, devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001042 uint8_t tmp;
1043
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001044 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001045 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001046 return -1;
1047 }
1048
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001049 /* Check for the ISA bridge first. */
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001050 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001051 switch (dev->device_id) {
1052 case 0x0030: /* CK804 */
1053 case 0x0050: /* MCP04 */
1054 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001055 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001056 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001057 case 0x0260: /* MCP51 */
Michael Karcher242efd42011-03-06 12:09:05 +00001058 case 0x0261: /* MCP51 */
Joshua Roys6e48a022012-06-29 23:07:14 +00001059 case 0x0360: /* MCP55 */
Michael Karcher2ead2e22010-06-01 16:09:06 +00001060 case 0x0364: /* MCP55 */
1061 /* find SMBus controller on *this* southbridge */
1062 /* The infamous Tyan S2915-E has two south bridges; they are
1063 easily told apart from each other by the class of the
1064 LPC bridge, but have the same SMBus bridge IDs */
1065 if (dev->func != 0) {
1066 msg_perr("MCP LPC bridge at unexpected function"
1067 " number %d\n", dev->func);
1068 return -1;
1069 }
1070
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001071#if PCI_LIB_VERSION >= 0x020200
Michael Karcher2ead2e22010-06-01 16:09:06 +00001072 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001073#else
1074 /* pciutils/libpci before version 2.2 is too old to support
1075 * PCI domains. Such old machines usually don't have domains
1076 * besides domain 0, so this is not a problem.
1077 */
1078 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
1079#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +00001080 if (!dev) {
1081 msg_perr("MCP SMBus controller could not be found\n");
1082 return -1;
1083 }
1084 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
1085 if (devclass != 0x0C05) {
1086 msg_perr("Unexpected device class %04x for SMBus"
1087 " controller\n", devclass);
1088 return -1;
1089 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001090 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001091 default:
Sean Nelson316a29f2010-05-07 20:09:04 +00001092 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001093 return -1;
1094 }
1095
1096 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
1097 base += 0xC0;
1098
1099 tmp = INB(base + gpio);
1100 tmp &= ~0x0F; /* null lower nibble */
1101 tmp |= 0x04; /* gpio -> output. */
1102 if (raise)
1103 tmp |= 0x01;
1104 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001105
1106 return 0;
1107}
1108
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001109/*
1110 * Suited for:
Stefan Taunera9cbbac2011-08-07 13:17:20 +00001111 * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51
Sean Nelson0a247512010-08-15 14:36:18 +00001112 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001113 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +00001114 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001115static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +00001116{
1117 return nvidia_mcp_gpio_set(0x00, 1);
1118}
1119
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001120/*
1121 * Suited for:
1122 * - abit KN8 Ultra: NVIDIA CK804
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001123 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001124static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001125{
1126 return nvidia_mcp_gpio_set(0x02, 0);
1127}
1128
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001129/*
1130 * Suited for:
Michael Karcher2842db32011-04-14 23:14:27 +00001131 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
Uwe Hermannead705f2010-08-15 15:26:30 +00001132 * - MSI K8N Neo4: NVIDIA CK804. TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html.
1133 * - MSI K8NGM2-L: NVIDIA MCP51
Joshua Roys6e48a022012-06-29 23:07:14 +00001134 * - MSI K9N SLI: NVIDIA MCP55
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001135 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001136static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001137{
1138 return nvidia_mcp_gpio_set(0x02, 1);
1139}
1140
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001141/*
1142 * Suited for:
Uwe Hermann83d349a2010-10-18 22:32:03 +00001143 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
Jonathan Kollaschf8db9592010-10-15 23:02:15 +00001144 */
1145static int nvidia_mcp_gpio4_raise(void)
1146{
1147 return nvidia_mcp_gpio_set(0x04, 1);
1148}
1149
1150/*
1151 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001152 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
1153 *
1154 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
1155 * board. We can't tell the SMBus logical devices apart, but we
1156 * can tell the LPC bridge functions apart.
1157 * We need to choose the SMBus bridge next to the LPC bridge with
1158 * ID 0x364 and the "LPC bridge" class.
1159 * b) #TBL is hardwired on that board to a pull-down. It can be
1160 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +00001161 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001162static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +00001163{
1164 return nvidia_mcp_gpio_set(0x05, 1);
1165}
1166
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001167/*
1168 * Suited for:
1169 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +00001170 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001171static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +00001172{
1173 return nvidia_mcp_gpio_set(0x08, 1);
1174}
1175
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001176/*
1177 * Suited for:
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +00001178 * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
Idwer Volleringd8a00a02011-06-13 16:58:54 +00001179 */
1180static int nvidia_mcp_gpio0a_raise(void)
1181{
1182 return nvidia_mcp_gpio_set(0x0a, 1);
1183}
1184
1185/*
1186 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001187 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001188 */
Michael Karcher51825082010-06-12 23:14:03 +00001189static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001190{
1191 return nvidia_mcp_gpio_set(0x0c, 1);
1192}
1193
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001194/*
1195 * Suited for:
1196 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +00001197 */
1198static int nvidia_mcp_gpio4_lower(void)
1199{
1200 return nvidia_mcp_gpio_set(0x04, 0);
1201}
1202
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001203/*
1204 * Suited for:
1205 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001206 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001207static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001208{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001209 return nvidia_mcp_gpio_set(0x10, 1);
1210}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001211
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001212/*
1213 * Suited for:
1214 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001215 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001216static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001217{
1218 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001219}
1220
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001221/*
1222 * Suited for:
1223 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001224 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001225static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001226{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001227 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001228}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001229
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001230/*
1231 * Suited for:
Michael Karcher242efd42011-03-06 12:09:05 +00001232 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1233 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
Joshua Roys2ee137f2010-09-07 17:52:09 +00001234 */
1235static int nvidia_mcp_gpio3b_raise(void)
1236{
1237 return nvidia_mcp_gpio_set(0x3b, 1);
1238}
1239
1240/*
1241 * Suited for:
Joshua Roysb992d342011-11-02 14:31:18 +00001242 * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55
1243 */
1244static int board_sun_ultra_40_m2(void)
1245{
1246 int ret;
1247 uint8_t reg;
1248 uint16_t base;
1249 struct pci_dev *dev;
1250
1251 ret = nvidia_mcp_gpio4_lower();
1252 if (ret)
1253 return ret;
1254
1255 dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */
1256 if (!dev) {
1257 msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n");
1258 return -1;
1259 }
1260
1261 base = pci_read_word(dev, 0xb4); /* some IO BAR? */
1262 if (!base)
1263 return -1;
1264
1265 reg = INB(base + 0x4b);
1266 reg |= 0x10;
1267 OUTB(reg, base + 0x4b);
1268
1269 return 0;
1270}
1271
1272/*
1273 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001274 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001275 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001276static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001277{
1278#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001279#define DBE6x_PRI_BOOT_LOC_SHIFT 2
1280#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1281#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001282#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1283#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1284#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001285#define DBE6x_BOOT_LOC_FLASH 2
1286#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001287
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001288 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001289 unsigned long boot_loc;
1290
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001291 /* Geode only has a single core */
1292 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001293 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001294
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001295 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001296
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001297 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001298 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1299 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1300 else
1301 boot_loc = DBE6x_BOOT_LOC_FLASH;
1302
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001303 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1304 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +00001305 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001306
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001307 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001308
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001309 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001310
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001311 return 0;
1312}
1313
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001314/*
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001315 * Suited for:
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001316 * - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001317 * Datasheet(s) used:
1318 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1319 */
1320static int amd_sbxxx_gpio9_raise(void)
1321{
1322 struct pci_dev *dev;
1323 uint32_t reg;
1324
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001325 dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001326 if (!dev) {
1327 msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1328 return -1;
1329 }
1330
1331 reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1332 /* enable output (0: enable, 1: tristate):
1333 GPIO9 output enable is at bit 5 in 0xA9 */
1334 reg &= ~((uint32_t)1<<(8+5));
1335 /* raise:
1336 GPIO9 output register is at bit 5 in 0xA8 */
1337 reg |= (1<<5);
1338 pci_write_long(dev, 0xA8, reg);
1339
1340 return 0;
1341}
1342
1343/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001344 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +00001345 */
1346static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1347{
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001348 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001349 struct pci_dev *dev;
1350 uint32_t tmp, base;
1351
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001352 /* GPO{0,8,27,28,30} are always available. */
1353 static const uint32_t nonmuxed_gpos = 0x58000101;
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001354
1355 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001356 {0},
1357 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1358 {0xB0, 0x0001, 0x0000},
1359 {0xB0, 0x0001, 0x0000},
1360 {0xB0, 0x0001, 0x0000},
1361 {0xB0, 0x0001, 0x0000},
1362 {0xB0, 0x0001, 0x0000},
1363 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1364 {0},
1365 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1366 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1367 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1368 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1369 {0x4E, 0x0100, 0x0000},
1370 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1371 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1372 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1373 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1374 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1375 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1376 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1377 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1378 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1379 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1380 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1381 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1382 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1383 {0},
1384 {0},
1385 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1386 {0}
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001387 };
1388
Luc Verhaegenf5226912009-12-14 10:41:58 +00001389 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1390 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001391 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001392 return -1;
1393 }
1394
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001395 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001396 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001397 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001398 return -1;
1399 }
1400
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001401 if ((((1 << gpo) & nonmuxed_gpos) == 0) &&
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001402 ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) !=
1403 piix4_gpo[gpo].value)) {
1404 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001405 return -1;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001406 }
1407
Luc Verhaegenf5226912009-12-14 10:41:58 +00001408 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1409 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001410 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001411 return -1;
1412 }
1413
1414 /* PM IO base */
1415 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1416
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001417 gpo_byte = gpo >> 3;
1418 gpo_bit = gpo & 7;
1419 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001420 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001421 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001422 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001423 tmp &= ~(0x01 << gpo_bit);
1424 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001425
1426 return 0;
1427}
1428
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001429/*
1430 * Suited for:
Joshua Roysd708fad2012-02-17 14:51:15 +00001431 * - ASUS OPLX-M
Mattias Mattsson85016b92010-09-01 01:21:34 +00001432 * - ASUS P2B-N
1433 */
1434static int intel_piix4_gpo18_lower(void)
1435{
1436 return intel_piix4_gpo_set(18, 0);
1437}
1438
1439/*
1440 * Suited for:
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001441 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1442 */
1443static int intel_piix4_gpo14_raise(void)
1444{
1445 return intel_piix4_gpo_set(14, 1);
1446}
1447
1448/*
1449 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001450 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001451 */
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001452static int intel_piix4_gpo22_raise(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001453{
1454 return intel_piix4_gpo_set(22, 1);
1455}
1456
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001457/*
1458 * Suited for:
Tim ter Laak4b933f02010-09-13 23:00:57 +00001459 * - abit BM6
1460 */
1461static int intel_piix4_gpo26_lower(void)
1462{
1463 return intel_piix4_gpo_set(26, 0);
1464}
1465
1466/*
1467 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001468 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001469 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001470static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001471{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001472 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001473}
1474
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001475/*
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001476 * Suited for:
1477 * - Dell OptiPlex GX1
1478 */
1479static int intel_piix4_gpo30_lower(void)
1480{
1481 return intel_piix4_gpo_set(30, 0);
1482}
1483
1484/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001485 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001486 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001487static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001488{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001489 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001490 static struct {
1491 uint16_t id;
1492 uint8_t base_reg;
1493 uint32_t bank0;
1494 uint32_t bank1;
1495 uint32_t bank2;
1496 } intel_ich_gpio_table[] = {
1497 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1498 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1499 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1500 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1501 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1502 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1503 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1504 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1505 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1506 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1507 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1508 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
1509 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1510 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1511 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1512 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1513 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1514 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1515 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1516 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1517 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1518 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1519 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1520 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1521 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1522 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1523 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1524 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1525 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1526 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1527 {0, 0, 0, 0, 0} /* end marker */
1528 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001529
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001530 struct pci_dev *dev;
1531 uint16_t base;
1532 uint32_t tmp;
1533 int i, allowed;
1534
1535 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001536 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001537 uint16_t device_class;
1538 /* libpci before version 2.2.4 does not store class info. */
1539 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001540 if ((dev->vendor_id == 0x8086) &&
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001541 (device_class == 0x0601)) { /* ISA bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001542 /* Is this device in our list? */
1543 for (i = 0; intel_ich_gpio_table[i].id; i++)
1544 if (dev->device_id == intel_ich_gpio_table[i].id)
1545 break;
1546
1547 if (intel_ich_gpio_table[i].id)
1548 break;
1549 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001550 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001551
Uwe Hermann93f66db2008-05-22 21:19:38 +00001552 if (!dev) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001553 msg_perr("\nERROR: No known Intel LPC bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001554 return -1;
1555 }
1556
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001557 /*
1558 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1559 * strapped to zero. From some mobile ICH9 version on, this becomes
1560 * 6:1. The mask below catches all.
1561 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001562 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001563
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001564 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001565 if (gpio < 32)
1566 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1567 else if (gpio < 64)
1568 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1569 else
1570 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1571
1572 if (!allowed) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001573 msg_perr("\nERROR: This Intel LPC bridge does not allow"
1574 " setting GPIO%02d\n", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001575 return -1;
1576 }
1577
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001578 msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",
1579 raise ? "Rais" : "Dropp", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001580
1581 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001582 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001583 tmp = INL(base);
1584 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1585 if ((gpio == 28) &&
1586 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1587 tmp |= 1 << 27;
1588 else
1589 tmp |= 1 << gpio;
1590 OUTL(tmp, base);
1591
1592 /* As soon as we are talking to ICH8 and above, this register
1593 decides whether we can set the gpio or not. */
1594 if (dev->device_id > 0x2800) {
1595 tmp = INL(base);
1596 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001597 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001598 " does not allow setting GPIO%02d\n",
1599 gpio);
1600 return -1;
1601 }
1602 }
1603
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001604 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001605 tmp = INL(base + 0x04);
1606 tmp &= ~(1 << gpio);
1607 OUTL(tmp, base + 0x04);
1608
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001609 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001610 tmp = INL(base + 0x0C);
1611 if (raise)
1612 tmp |= 1 << gpio;
1613 else
1614 tmp &= ~(1 << gpio);
1615 OUTL(tmp, base + 0x0C);
1616 } else if (gpio < 64) {
1617 gpio -= 32;
1618
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001619 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001620 tmp = INL(base + 0x30);
1621 tmp |= 1 << gpio;
1622 OUTL(tmp, base + 0x30);
1623
1624 /* As soon as we are talking to ICH8 and above, this register
1625 decides whether we can set the gpio or not. */
1626 if (dev->device_id > 0x2800) {
1627 tmp = INL(base + 30);
1628 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001629 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001630 " does not allow setting GPIO%02d\n",
1631 gpio + 32);
1632 return -1;
1633 }
1634 }
1635
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001636 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001637 tmp = INL(base + 0x34);
1638 tmp &= ~(1 << gpio);
1639 OUTL(tmp, base + 0x34);
1640
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001641 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001642 tmp = INL(base + 0x38);
1643 if (raise)
1644 tmp |= 1 << gpio;
1645 else
1646 tmp &= ~(1 << gpio);
1647 OUTL(tmp, base + 0x38);
1648 } else {
1649 gpio -= 64;
1650
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001651 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001652 tmp = INL(base + 0x40);
1653 tmp |= 1 << gpio;
1654 OUTL(tmp, base + 0x40);
1655
1656 tmp = INL(base + 40);
1657 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001658 msg_perr("\nERROR: This Intel LPC bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001659 "not allow setting GPIO%02d\n", gpio + 64);
1660 return -1;
1661 }
1662
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001663 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001664 tmp = INL(base + 0x44);
1665 tmp &= ~(1 << gpio);
1666 OUTL(tmp, base + 0x44);
1667
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001668 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001669 tmp = INL(base + 0x48);
1670 if (raise)
1671 tmp |= 1 << gpio;
1672 else
1673 tmp &= ~(1 << gpio);
1674 OUTL(tmp, base + 0x48);
1675 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001676
1677 return 0;
1678}
1679
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001680/*
1681 * Suited for:
1682 * - abit IP35: Intel P35 + ICH9R
1683 * - abit IP35 Pro: Intel P35 + ICH9R
Joshua Roysac8b2a12011-08-11 04:21:34 +00001684 * - ASUS P5LD2
Uwe Hermann93f66db2008-05-22 21:19:38 +00001685 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001686static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001687{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001688 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001689}
1690
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001691/*
1692 * Suited for:
1693 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001694 */
1695static int intel_ich_gpio18_raise(void)
1696{
1697 return intel_ich_gpio_set(18, 1);
1698}
1699
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001700/*
1701 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001702 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001703 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001704static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001705{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001706 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001707}
1708
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001709/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001710 * Suited for:
Stefan Tauner027e0182012-05-02 19:48:21 +00001711 * - ASUS P5BV-R: LGA775 + 3200 + ICH7
1712 */
1713static int intel_ich_gpio20_raise(void)
1714{
1715 return intel_ich_gpio_set(20, 1);
1716}
1717
1718/*
1719 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001720 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1721 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
Michael Karcherf4b58792010-09-10 14:54:18 +00001722 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001723 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
Diego Elio Pettenòc6f71462011-03-06 22:52:55 +00001724 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
Michael Karcher4a23e442010-09-10 14:46:46 +00001725 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00001726 * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R
Joshua Roysb1d980f2010-09-13 14:02:22 +00001727 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001728 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
Stefan Taunerded71e52012-03-10 19:22:13 +00001729 * - ASUS TUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001730 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001731 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001732static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001733{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001734 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001735}
1736
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001737/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001738 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001739 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001740 * - ASUS P4B533-E: socket478 + 845E + ICH4
1741 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Michael Karcherbfd89a52012-02-12 00:13:14 +00001742 * - TriGem Anaheim-3: socket370 + Intel 810 + ICH
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001743 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001744static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001745{
1746 return intel_ich_gpio_set(22, 1);
1747}
1748
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001749/*
1750 * Suited for:
Stefan Tauner716e0982011-07-25 20:38:52 +00001751 * - ASUS A8Jm (laptop): Intel 945 + ICH7
Michael Karcher14ab8d42011-08-25 14:06:50 +00001752 * - ASUS P5LP-LE used in ...
1753 * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E"
1754 * - Epson Endeavor MT7700
Stefan Tauner716e0982011-07-25 20:38:52 +00001755 */
1756static int intel_ich_gpio34_raise(void)
1757{
1758 return intel_ich_gpio_set(34, 1);
1759}
1760
1761/*
1762 * Suited for:
Stefan Taunerc6782182012-01-19 17:50:32 +00001763 * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ...
Paul Menzelac427b22012-02-16 21:07:07 +00001764 * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1)
Stefan Taunerc6782182012-01-19 17:50:32 +00001765 */
1766static int intel_ich_gpio38_raise(void)
1767{
1768 return intel_ich_gpio_set(38, 1);
1769}
1770
1771/*
1772 * Suited for:
Joshua Roysc73e2812011-07-09 19:46:53 +00001773 * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
1774 */
1775static int intel_ich_gpio43_raise(void)
1776{
1777 return intel_ich_gpio_set(43, 1);
1778}
1779
1780/*
1781 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001782 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001783 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001784static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001785{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001786 int ret;
1787 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1788 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001789 ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001790 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001791 ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */
1792 return ret;
1793}
1794
1795/*
1796 * Suited for:
1797 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1798 */
1799static int board_hp_p2706t(void)
1800{
1801 int ret;
1802 ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1803 if (!ret)
1804 ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001805 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001806}
1807
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001808/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001809 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001810 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1811 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1812 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Uwe Hermann742999c2010-12-02 21:57:42 +00001813 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001814 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001815static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001816{
1817 return intel_ich_gpio_set(23, 1);
1818}
1819
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001820/*
1821 * Suited for:
Michael Karcher39dcdec2010-10-05 17:29:35 +00001822 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001823 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001824 */
1825static int intel_ich_gpio25_raise(void)
1826{
1827 return intel_ich_gpio_set(25, 1);
1828}
1829
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001830/*
1831 * Suited for:
1832 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001833 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001834static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001835{
1836 return intel_ich_gpio_set(26, 1);
1837}
1838
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001839/*
1840 * Suited for:
1841 * - P4SD-LA (HP OEM): i865 + ICH5
Joshua Roys9d9a1042011-06-13 16:59:01 +00001842 * - GIGABYTE GA-8IP775: 865P + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001843 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Maciej Pijanka6add0942011-06-09 20:59:30 +00001844 * - MSI MS-6788-40 (aka 848P Neo-V)
Michael Karcher87c90992010-07-24 11:03:48 +00001845 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001846static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001847{
1848 return intel_ich_gpio_set(32, 1);
1849}
1850
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001851/*
1852 * Suited for:
Joshua Roys7225ccd2011-05-18 01:32:16 +00001853 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1854 */
1855static int board_aopen_i975xa_ydg(void)
1856{
1857 int ret;
1858
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001859 /* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,
Joshua Roys7225ccd2011-05-18 01:32:16 +00001860 * or perhaps it's not needed at all?
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001861 * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1862 * were in the right LDN, it would have to be GPIO1 or GPIO3.
Joshua Roys7225ccd2011-05-18 01:32:16 +00001863 */
1864/*
1865 ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1866 if (!ret)
1867*/
1868 ret = intel_ich_gpio_set(33, 1);
1869
1870 return ret;
1871}
1872
1873/*
1874 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001875 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001876 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001877static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001878{
1879 int ret;
1880
1881 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1882 ret = intel_ich_gpio_set(22, 1);
1883 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1884 ret = intel_ich_gpio_set(23, 1);
1885
1886 return ret;
1887}
1888
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001889/*
1890 * Suited for:
1891 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001892 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001893static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001894{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001895 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001896
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001897 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1898 if (!ret)
1899 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001900
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001901 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001902}
1903
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001904/*
1905 * Suited for:
1906 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001907 */
Michael Karcher06477332010-03-19 22:49:09 +00001908static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001909{
Michael Karcher06477332010-03-19 22:49:09 +00001910 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001911 uint32_t base, tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001912
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001913 /* VT82C686 power management */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001914 dev = pci_dev_find(0x1106, 0x3057);
1915 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001916 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001917 return -1;
1918 }
1919
Sean Nelson316a29f2010-05-07 20:09:04 +00001920 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001921 raise ? "Rais" : "Dropp", gpio);
Michael Karcher06477332010-03-19 22:49:09 +00001922
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001923 /* Select GPO function on multiplexed pins. */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001924 tmp = pci_read_byte(dev, 0x54);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001925 switch (gpio) {
1926 case 0:
1927 tmp &= ~0x03;
1928 break;
1929 case 1:
1930 tmp |= 0x04;
1931 break;
1932 case 2:
1933 tmp |= 0x08;
1934 break;
1935 case 3:
1936 tmp |= 0x10;
1937 break;
Michael Karcher06477332010-03-19 22:49:09 +00001938 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001939 pci_write_byte(dev, 0x54, tmp);
1940
1941 /* PM IO base */
1942 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1943
1944 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001945 tmp = INL(base + 0x4C);
1946 if (raise)
1947 tmp |= 1U << gpio;
1948 else
1949 tmp &= ~(1U << gpio);
1950 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001951
1952 return 0;
1953}
1954
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001955/*
1956 * Suited for:
1957 * - abit VT6X4: Pro133x + VT82C686A
Mattias Mattssone3df96e2010-08-15 22:43:23 +00001958 * - abit VA6: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001959 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001960static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00001961{
1962 return via_apollo_gpo_set(4, 0);
1963}
1964
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001965/*
1966 * Suited for:
1967 * - Soyo SY-7VCA: Pro133A + VT82C686
Michael Karcher06477332010-03-19 22:49:09 +00001968 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001969static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00001970{
1971 return via_apollo_gpo_set(0, 0);
1972}
1973
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001974/*
Michael Karchera08d0f22011-07-25 17:25:24 +00001975 * Enable some GPIO pin on SiS southbridge and enables SIO flash writes.
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001976 *
1977 * Suited for:
1978 * - MSI 651M-L: SiS651 / SiS962
Michael Karchera08d0f22011-07-25 17:25:24 +00001979 * - GIGABYTE GA-8SIMLH
Michael Karcher9f9e6132010-01-09 17:36:06 +00001980 */
Michael Karchera08d0f22011-07-25 17:25:24 +00001981static int sis_gpio0_raise_and_w836xx_memw(void)
Michael Karcher9f9e6132010-01-09 17:36:06 +00001982{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001983 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001984 uint16_t base, temp;