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review.coreboot.org / coreboot / fe7b5d2fa6705a2b553244dda0452ca55c5730a2 / src / northbridge
  1. fe7b5d2 Ivybridge: fix workaround and enable PAIR by Duncan Laurie · 12 years ago
  2. 77dbbac CPU: Add basic support for Nominal Configurable TDP by Duncan Laurie · 12 years ago
  3. b91a0f2 Rename cache_lbmem() to cache_ramstage() by Stefan Reinauer · 12 years ago
  4. 6097e19 Make ACPI code detect Sandy/Ivy Bridge dynamically by Stefan Reinauer · 12 years ago
  5. afcaac2 Drop (empty) sandybridge_late_initialization() by Stefan Reinauer · 12 years ago
  6. baae2d2 Add support for HM70 and NM70 LPC bridge by Stefan Reinauer · 12 years ago
  7. 542e962 Print PCI ID of PCH during boot up by Stefan Reinauer · 12 years ago
  8. c664387 Drop leading spaces from CPU name string by Stefan Reinauer · 12 years ago
  9. 4821489 Fix MRC cache update delays by Stefan Reinauer · 12 years ago
  10. 496f4a0 SandyBridge: Add another PCI device ID for northbridge by Walter Murphy · 12 years ago
  11. da83a5f Fixes to enable RC6 on IvyBridge by Duncan Laurie · 12 years ago
  12. ce6e9fe i945: Disable IGD if plugin VGA is preferred by Patrick Georgi · 12 years ago
  13. 6db7f34 Trinity wrapper code improvement. by zbao · 12 years ago
  14. 8bacc40 Fix udelay() implementation for i945 romstage by Nico Huber · 12 years ago
  15. bcdbe90 Drop VGA_BRIDGE_SETUP config option by Patrick Georgi · 12 years ago
  16. cda9f93 Intel SCH northbridge: fix resource index by Kyösti Mälkki · 12 years ago
  17. 1171986 Drop invalid device ops on Agesa northbridge by Kyösti Mälkki · 12 years ago
  18. de3dde4 AMD: Fix GFXUMA with 4GB or more RAM by Kyösti Mälkki · 12 years ago
  19. ba589e3 Move setup_uma_memory() to K8 northbridge by Kyösti Mälkki · 12 years ago
  20. 231f261 Move setup_uma_memory() to AMDFAM10 northbridge by Kyösti Mälkki · 12 years ago
  21. 55fff930 Move setup_uma_memory() to Agesa Family14 northbridge by Kyösti Mälkki · 12 years ago
  22. d4821fc Move setup_uma_memory() to Agesa Family12 northbridge by Kyösti Mälkki · 12 years ago
  23. 03548aa Move setup_uma_memory() to Agesa Family15 northbridge by Kyösti Mälkki · 12 years ago
  24. cc55b9b Define global uma_memory variables by Kyösti Mälkki · 12 years ago
  25. 63f8c08 Add global uma_resource() by Kyösti Mälkki · 12 years ago
  26. d422069 i5000: Fix resource allocation by Sven Schnelle · 12 years ago
  27. 34d86f0 i5000: reset system if raminit fails by Sven Schnelle · 12 years ago
  28. 7b48379 i5000: Add PCI ids for all i5000 flavours by Sven Schnelle · 12 years ago
  29. 6444bd4 i945: Reset IGD on boot by Patrick Georgi · 12 years ago
  30. 2c08f6a AGESA F15 wrapper for Trinity by zbao · 12 years ago
  31. 904a0ec Don't use 64-bit constant 0x100000000 in linker scripts by Nico Huber · 12 years ago
  32. 1454685 i5000: fix another typo by Sven Schnelle · 12 years ago
  33. 39b47d2 i5000: fix typos by Sven Schnelle · 12 years ago
  34. 1a7a7e6 i5000: enforce hard reset by Sven Schnelle · 12 years ago
  35. 88fc0b9 Sandybridge: Remove remnants of FDT support from MRC cache code by Stefan Reinauer · 12 years ago
  36. 6e901fd Sandybridge: Fix MRC cache calculation by Stefan Reinauer · 12 years ago
  37. 2f00ce3 cbtypes.h: Unify cbtypes.h used in AMD board's code by Vikram Narayanan · 12 years ago
  38. bb11e60 Hook up MRC cache update by Stefan Reinauer · 12 years ago
  39. 1244f4b Rework Sandybridge MRC cache handling by Stefan Reinauer · 12 years ago
  40. f8f0062 Some more #if cleanup by Patrick Georgi · 12 years ago
  41. e166782 Clean up #ifs by Patrick Georgi · 12 years ago
  42. f125d80 Add missing newline to printk in Sandybridge init code by Stefan Reinauer · 12 years ago
  43. adc05c1 Make Intel i5000 specific options only appear on i5000 systems by Stefan Reinauer · 12 years ago
  44. cafedcf Strip quotes from Sandybridge MRC blob by Stefan Reinauer · 12 years ago
  45. 7a3f36a Sandybridge: Display platform information early by Vadim Bendebury · 12 years ago
  46. 8508cff Update Ivybridge GT power meter tables by Duncan Laurie · 12 years ago
  47. dd585b8 Update ivybridge graphics initialization by Duncan Laurie · 12 years ago
  48. 7b508dd Only send ME Dram Init Done message on Sandybridge by Duncan Laurie · 12 years ago
  49. 0ff99b7 Modify DMI init for IvyBridge by Vincent Palatin · 12 years ago
  50. e6063fe Fix Sandybridge/Ivybridge mainboards according to code review by Stefan Reinauer · 12 years ago
  51. 6ea86b1 Sandybridge: Temporarily disable MRC cache finding code by Stefan Reinauer · 12 years ago
  52. a403c68 Add default map_oprom_vendev() for AMD Family 14h processors. by Martin Roth · 12 years ago
  53. e9dfdd9 Reverse Vendor ID & Device ID for map_oprom_vendev() by Martin Roth · 12 years ago
  54. 16401b8 SMM: Add udelay on Sandybridge systems by Stefan Reinauer · 12 years ago
  55. 93b4ed9 Intel e7505: build as separate object file by Kyösti Mälkki · 12 years ago
  56. 97c064f Intel e7505: enable ECC scrubbing by Kyösti Mälkki · 12 years ago
  57. 26b00e6 Refactor some alignment handling by Patrick Georgi · 12 years ago
  58. 77e4f7d Intel e7505: refactor only by Kyösti Mälkki · 12 years ago
  59. 26c7b86 Intel e7505: handlers for undocumented registers by Kyösti Mälkki · 12 years ago
  60. f722373 S3 code in coreboot public folder. by zbao · 12 years ago
  61. 2c2e78d Unify IO APIC address specification by Patrick Georgi · 13 years ago
  62. 5c1ff92 Intel e7505: cleanups by Kyösti Mälkki · 12 years ago
  63. 5bd271b Intel e7505: renames only by Kyösti Mälkki · 12 years ago
  64. cab72d9 amdfam10: add phenom II as known cpu by Bernhard Urban · 12 years ago
  65. 00636b0 Add support for Intel Sandybridge CPU (northbridge part) by Stefan Reinauer · 12 years ago
  66. c0c5ac7 Add the support for RDC R8610 Northbridge by Rudolf Marek · 12 years ago
  67. dd3b227 Fix AMD Fam15 CBMEM allocation by Stefan Reinauer · 12 years ago
  68. 30b46ce Fix AMD Fam12 CBMEM allocation by Stefan Reinauer · 12 years ago
  69. cc6c615 Fix AMD Fam10 CBMEM allocation by Stefan Reinauer · 12 years ago
  70. 3ae1c65 AMD Agesa: delete no-op bootblock files by Kyösti Mälkki · 12 years ago
  71. d11ca1d Rename AMD_AGESA to CPU_AMD_AGESA by Kyösti Mälkki · 12 years ago
  72. f5bb477 Fix AMD Agesa leaking Kconfig by Kyösti Mälkki · 12 years ago
  73. eb5e28f Intel northbridge I945: Apply un-written naming rules by Kyösti Mälkki · 12 years ago
  74. 35e1c86 VIA southbridge K8T890: Apply un-written naming rules by Kyösti Mälkki · 12 years ago
  75. 5750ed2 Fix AMD Fam14 cbmen allocation by Marc Jones · 12 years ago
  76. 8d59569 Clean up whitespace in fam14 northbridge.c by Marc Jones · 12 years ago
  77. c5fc7db Move C labels to start-of-line by Patrick Georgi · 12 years ago
  78. 067d223 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. by Marc Jones · 12 years ago
  79. 334328a Avoid ../../.. paths in ASL files by Patrick Georgi · 13 years ago
  80. fdcd135 Rename i945 ACPI files to not carry an i945_ prefix by Patrick Georgi · 13 years ago
  81. 472efa6 Remove whitespace. by Patrick Georgi · 13 years ago
  82. 6811f75 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper by Kerry Sheh · 13 years ago
  83. 6b909f2 RD890: AMD RD890/SR56X0 CIMX wrapper by Kerry Sheh · 13 years ago
  84. bdc8c83 Remove non-existent include by Sven Schnelle · 13 years ago
  85. 332a7e9 i5000: halt second BSP by Sven Schnelle · 13 years ago
  86. 1767086 Add Intel i5000 Memory Controller Hub by Sven Schnelle · 13 years ago
  87. 751508a northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option by Peter Stuge · 13 years ago
  88. 976f8cc Make Geode GX2 VGA setup work. by Nils Jacobs · 13 years ago
  89. 784ffb3 i945: fix tsc udelay() by Sven Schnelle · 13 years ago
  90. d0ac789 Update geode GX2 tree to match LX. by Nils Jacobs · 13 years ago
  91. 84e0dfc Clean up AMD Fam14 SSDT by Marc Jones · 13 years ago
  92. a4f06f1 White space and coding style fixes. by Nils Jacobs · 13 years ago
  93. 36b53bf k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x by Florian Zumbiehl · 13 years ago
  94. 2a830d0 Change AMD vendorcode build by Kyösti Mälkki · 13 years ago
  95. fa48b96 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 by Florian Zumbiehl · 13 years ago
  96. 6f7b158 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit by Florian Zumbiehl · 13 years ago
  97. 7e9de01 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 by Florian Zumbiehl · 13 years ago
  98. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 13 years ago
  99. 0a0d5e8 Add support for E7505 northbridge. by Kyösti Mälkki · 13 years ago
  100. 481814d Clear improper use of CONFIG_CACHE_AS_RAM by Kyösti Mälkki · 13 years ago