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review.coreboot.org / coreboot / bf396ff21c60f364e5d0af4eda1e38f4603fc3b1 / src / cpu / intel
  1. bf396ff haswell: use s3_resume field in romstage_handoff by Aaron Durbin · 12 years ago
  2. ef4275b x86: protect against abi assumptions from compiler by Aaron Durbin · 12 years ago
  3. e2d9e5b haswell: support for CONFIG_RELOCATABLE_RAMSTAGE by Aaron Durbin · 12 years ago
  4. a146d58 ramstage: prepare for relocation by Aaron Durbin · 12 years ago
  5. 2c3f161 Intel: Update CPU microcode for Sandybridge/Ivybridge CPUs by Stefan Reinauer · 11 years ago
  6. 511c4b7 Intel: Update CPU microcode for 1067x CPUs by Stefan Reinauer · 11 years ago
  7. 8c20399 haswell: wait 10ms after INIT IPI by Aaron Durbin · 12 years ago
  8. 305b1f0 haswell: Parallel AP bringup by Aaron Durbin · 12 years ago
  9. 98ffb42 intel microcode: split up microcode loading stages by Aaron Durbin · 12 years ago
  10. 7492ec1 haswell: add romstage_after_car() function by Aaron Durbin · 12 years ago
  11. 2ad1dba haswell: move call site of save_mrc_data() by Aaron Durbin · 12 years ago
  12. 38d9423 haswell: romstage: pass stack pointer and MTRRs by Aaron Durbin · 12 years ago
  13. a267161 haswell: unify romstage logic by Aaron Durbin · 12 years ago
  14. 3d0071b haswell: adjust CAR usage by Aaron Durbin · 12 years ago
  15. 7af2069 haswell: enable caching before SMM initialization by Aaron Durbin · 12 years ago
  16. 24614af haswell: Clear correct number of MCA banks by Aaron Durbin · 12 years ago
  17. a416bfe haswell: move definition of CORE_THREAD_COUNT_MSR by Aaron Durbin · 12 years ago
  18. 29ffa54 haswell: Use SMM Modules by Aaron Durbin · 12 years ago
  19. 6dccedd x86 intel: Add Firmware Interface Table support by Aaron Durbin · 12 years ago
  20. 51254049 haswell: Add ULT CPUID and updated microcode by Duncan Laurie · 12 years ago
  21. dc278f8 haswell: Properly Guard Engergy Policy by CPUID by Aaron Durbin · 12 years ago
  22. 76c3700 haswell: Add initial support for Haswell platforms by Aaron Durbin · 12 years ago
  23. 5a22b14 Fix socket LGA775 by Kyösti Mälkki · 11 years ago
  24. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  25. 0aa37c4 sconfig: rename lapic_cluster -> cpu_cluster by Stefan Reinauer · 12 years ago
  26. 8cc8468 Intel: Replace MSR 0xcd with MSR_FSB_FREQ by Patrick Georgi · 12 years ago
  27. 644e83b speedstep: Deduplicate some MSR identifiers by Patrick Georgi · 12 years ago
  28. 223af0d document Intel VMX locking behavior by Mike Frysinger · 12 years ago
  29. 6fe0cab Extend CBFS to support arbitrary ROM source media. by Hung-Te Lin · 12 years ago
  30. 23f38cd Get rid of drivers class by Patrick Georgi · 12 years ago
  31. a42e2f4 Add spinlock to serialize Intel microcode updates by Stefan Reinauer · 12 years ago
  32. 455f4b4 Fix CONFIG_MAX_CPU set to 1 CPU build problem by Stefan Reinauer · 12 years ago
  33. 08067ba ivybridge: Catch unknown CPU revisions by Stefan Reinauer · 12 years ago
  34. f5a11aa Initialize the VMX MSR by Marc Jones · 12 years ago
  35. 5986eda Revert "Remove code that enables/disables VMX in coreboot on chromebooks." by Marc Jones · 12 years ago
  36. bb9dff5 sandybridge: Correct reporting of cores and threads by Stefan Reinauer · 12 years ago
  37. d16d576 Leave power control registers unlocked by Sameer Nanda · 12 years ago
  38. 68d7c7a cpu/intel/model_1067x: Add proper c-state/p-state/thermal support by Nico Huber · 12 years ago
  39. bf10bc3 intel/socket_BGA956: enable speedstep, CAR, MMX, SSE by Patrick Georgi · 12 years ago
  40. a74af56 Overhaul speedstep code by Nico Huber · 12 years ago
  41. 252d39b Fix some indentation flaws and break very long lines by Nico Huber · 12 years ago
  42. ad874e3 Correct FSB reading in speedstep ACPI by Nico Huber · 12 years ago
  43. 41392df Merge cpu/intel/acpi.h into cpu/intel/speedstep.h by Nico Huber · 12 years ago
  44. bef3d34 Add support for socket LGA775 by Stefan Tauner · 12 years ago
  45. e5fe3ac Fix typo in mPGA603 socket by Kyösti Mälkki · 12 years ago
  46. 0279036 Remove chip.h files without config structure by Kyösti Mälkki · 12 years ago
  47. 00b579a buildsystem: Make CPU microcode updating more configurable by Alexandru Gagniuc · 12 years ago
  48. 0a78f91 Intel model_106cx: change CAR to HT-capable by Kyösti Mälkki · 12 years ago
  49. fee73df Auto-declare chip_operations by Kyösti Mälkki · 12 years ago
  50. 0db6820 Synchronize rdtsc instructions by Stefan Reinauer · 12 years ago
  51. df0fbc7 Intel CPUs: Fix counting of CPU cores by Kyösti Mälkki · 12 years ago
  52. 51676b1 Revert "Use broadcast SIPI to startup siblings" by Sven Schnelle · 12 years ago
  53. a2701c6 Revert "remove CONFIG_SERIAL_CPU_INIT" by Sven Schnelle · 12 years ago
  54. 5563211 CPU: Add option to set TCC activation offset by Duncan Laurie · 12 years ago
  55. d6aca0b ACPI: Add a method to notify OS to re-read _PPC by Duncan Laurie · 12 years ago
  56. 0eefa00 ACPI: Add function to write _PPC using NVS by Duncan Laurie · 12 years ago
  57. 0b7b7b6 Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs by Stefan Reinauer · 12 years ago
  58. c65a36e Enable Microcode in CBFS for all SandyBridge/IvyBridge systems by Stefan Reinauer · 12 years ago
  59. c0f2cfb Fix comment to reference IvyBridge, too by Stefan Reinauer · 12 years ago
  60. 6d29c73 Include SandyBridge Microcode when IvyBridge is enabled by Stefan Reinauer · 12 years ago
  61. 0aa5b09 Fix date output in Microcode update by Stefan Reinauer · 12 years ago
  62. 22935e1 CPU: Set flex ratio to nominal TDP ratio in bootblock by Duncan Laurie · 12 years ago
  63. 4e4320f CPU: Update ivybridge PP1 current limit value by Duncan Laurie · 12 years ago
  64. 77dbbac CPU: Add basic support for Nominal Configurable TDP by Duncan Laurie · 12 years ago
  65. 999e94c Config changes to support microcode in CBFS by Vadim Bendebury · 12 years ago
  66. 39fea6e Add microcode blob processing by Vadim Bendebury · 12 years ago
  67. 537b4e0 Add code to read Intel microcode from CBFS by Vadim Bendebury · 12 years ago
  68. df0c822 Rename microcode include file to be model agnostic by Vadim Bendebury · 12 years ago
  69. b38e0c3 Properly identify ACPI C3 states in _CST table. by Duncan Laurie · 12 years ago
  70. 305b19d Remove code that enables/disables VMX in coreboot on chromebooks. by Ronald G. Minnich · 12 years ago
  71. 5458b9d Intel cpus: Extend cache to cover complete Flash Device by Kyösti Mälkki · 12 years ago
  72. ae7d6ef Intel model_106cx: change CAR to model_6ex by Kyösti Mälkki · 12 years ago
  73. 4dcc573 Intel cpus: delete dead CAR code and whitespace fixes by Kyösti Mälkki · 12 years ago
  74. c7fb2ae Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR by Kyösti Mälkki · 12 years ago
  75. 78efc4c remove CONFIG_SERIAL_CPU_INIT by Sven Schnelle · 12 years ago
  76. 042c146 Use broadcast SIPI to startup siblings by Sven Schnelle · 12 years ago
  77. 9ed1456 Intel CPUs: execute microcode update only once per core by Kyösti Mälkki · 12 years ago
  78. edac28c Enable Intel PECI on Model 6fx CPUs by Sven Schnelle · 12 years ago
  79. bb31f3a Drop config variable CPU_MODEL_INDEX by Stefan Reinauer · 12 years ago
  80. e166782 Clean up #ifs by Patrick Georgi · 12 years ago
  81. 3b5a9ed Fix register corruption during Intel Microcode update by Stefan Reinauer · 12 years ago
  82. 252111d Don't include console.h in microcode.c when compiling with ROMCC by Stefan Reinauer · 12 years ago
  83. c31384e Fix up Sandybridge C state generation code by Stefan Reinauer · 12 years ago
  84. 4cc8c70 Rework ACPI CST table generation by Stefan Reinauer · 12 years ago
  85. 3110945 microcode: print date of microcode and unify output by Stefan Reinauer · 12 years ago
  86. 3f8989e Revamp Intel microcode update code by Stefan Reinauer · 12 years ago
  87. 05e740f Replace cache control magic numbers with symbols by Patrick Georgi · 12 years ago
  88. f8c7c23 Fix support for RAM-less multi-processor init by Kyösti Mälkki · 12 years ago
  89. 5c55463 Add support for Intel Sandybridge CPU by Stefan Reinauer · 12 years ago
  90. ea37a21 Add support for Intel Turbo Boost feature by Stefan Reinauer · 12 years ago
  91. abdf15f Apply cache-as-ram conditionally on socket mPGA604 by Kyösti Mälkki · 12 years ago
  92. 819c7d4 Whitespace fixes by Patrick Georgi · 12 years ago
  93. a860c68 Intel cpus: get MAXPHYADDR at runtime for new CAR by Kyösti Mälkki · 12 years ago
  94. 0078ceb Intel cpus: add hyper-threading CPU support to new CAR by Kyösti Mälkki · 12 years ago
  95. 05d6ffb Intel cpus: improve CPU compatibility of new CAR by Kyösti Mälkki · 13 years ago
  96. f9d1a42 Intel cpus: apply some good programming practices in new CAR by Kyösti Mälkki · 12 years ago
  97. 325b92f Intel cpus: cache actual size of the Flash ROM device by Kyösti Mälkki · 12 years ago
  98. 5a660ca Intel cpus: copy model_6ex CAR code by Kyösti Mälkki · 12 years ago
  99. 8b28d50 Intel cpus: Fix deadlock on hyper-threading init by Kyösti Mälkki · 12 years ago
  100. 7a39446 Intel cpus: Include CAR from socket by Kyösti Mälkki · 13 years ago