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review.coreboot.org / coreboot / bc518d5cab4234a0d0d06a7d3829bbca9e318ba6 / src / northbridge
  1. a090ae0 nb/intel/x4x: Add DMI/EP init by Damien Zammit · 8 years ago
  2. 8f3aaa8 Fix leaking CONFIG_VGA=y by Kyösti Mälkki · 8 years ago
  3. 4bab6e7 intel/sch: Merge northbridge and southbridge in src/soc by Stefan Reinauer · 8 years ago
  4. 84da72c nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structure by Timothy Pearson · 8 years ago
  5. d112f46 nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15h by Timothy Pearson · 8 years ago
  6. 66fbeae intel/pineview: Don't try to store 34 bits in 32 by Stefan Reinauer · 8 years ago
  7. 617536e amd/gx2 + amd/lx: Fix shift overflow issue by Stefan Reinauer · 8 years ago
  8. 3b0f20b rdc/r8610: Move to src/soc by Stefan Reinauer · 8 years ago
  9. 5caf89b dmp/vortex86ex: Merge northbridge and southbridge into soc by Stefan Reinauer · 8 years ago
  10. 9c9bde3 nb/intel/sandybridge/raminit: support calling dram_freq multiple times by Patrick Rudolph · 8 years ago
  11. 2ccb74b nb/intel/sandybridge/raminit: add additional fallbacks by Patrick Rudolph · 8 years ago
  12. 1e302cb nb/intel/gm45: Fix native text mode initialization by Nick High · 8 years ago
  13. 394041b nb/amd/mct_ddr3: Only initialize ECC bits once by Timothy Pearson · 8 years ago
  14. ac6bd5b0 nb/amd/mct_ddr3: Warn if MaxRdLatency training fails on Family 15h by Timothy Pearson · 8 years ago
  15. 2bb1d30 nb/amd/mct_ddr3: Stop receiver enable cycle training after window found by Timothy Pearson · 8 years ago
  16. 29dd5da nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0 by Timothy Pearson · 8 years ago
  17. 263c679 nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4 by Timothy Pearson · 8 years ago
  18. 7f731f8 nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15h by Timothy Pearson · 8 years ago
  19. 588ccaa nb/intel/sandybridge/raminit: fix regression "always use mrccache" by Patrick Rudolph · 8 years ago 4.4 4.4
  20. 09e3bfb nb/amd/mct_ddr3: Restart system on training failure instead of using die() by Timothy Pearson · 8 years ago
  21. 0739b9f nb/amd/mct_ddr3: Report correct DIMM in MRS setup routines by Timothy Pearson · 8 years ago
  22. 3242bcf nb/amd/mct_ddr3: Fix a number of minor errors in RDIMM setup by Timothy Pearson · 8 years ago
  23. 4488d73 nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change by Timothy Pearson · 8 years ago
  24. 8b9c807 Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training" by Timothy Pearson · 8 years ago
  25. 5a35936 nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change by Timothy Pearson · 8 years ago
  26. 4901601 nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs by Timothy Pearson · 8 years ago
  27. b474afd nb/amd/mct_ddr3: Run fence training on each node after memory clock change by Timothy Pearson · 8 years ago
  28. 318e2ac AMD CIMX: Drop unused code by Kyösti Mälkki · 8 years ago
  29. 86ddd73 kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme by Stefan Reinauer · 8 years ago
  30. 5949371 northbridge/amd/{lx,gx2}: remove immediate accesses of 0 by Patrick Georgi · 8 years ago
  31. 46f8bd7 amd/agesa/family12/dimmSpd.c: Indent (tab) fix by Edward O'Callaghan · 10 years ago
  32. 186b9de and/nb/mct_ddr3: Pack all structures passed to ramstage and set alignment by Timothy Pearson · 8 years ago
  33. 54e0551 nb/amd/amdfam10: Write MCT variables to flash after PCI configuration by Timothy Pearson · 8 years ago
  34. 56abd4d nb/intel/sandybridge/raminit: always use mrccache by Patrick Rudolph · 8 years ago
  35. 5a57725 Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed" by Timothy Pearson · 8 years ago
  36. ba817d0 nb/amd/mct_ddr3: Reenable sync flood after ECC init by Timothy Pearson · 8 years ago
  37. 1d9370b nb/amd/mct_ddr3: Add MCE reporting logic by Timothy Pearson · 8 years ago
  38. 49e917b nb/amd/amdfam10: Only flag machine check exception if valid bit is set by Timothy Pearson · 8 years ago
  39. c5c3d76 nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform level by Timothy Pearson · 8 years ago
  40. 31d1959 nb/intel/sandybridge/raminit: die in toplevel function by Patrick Rudolph · 8 years ago
  41. 24a845b nb/intel/sandybridge/raminit: prepare raminit for fallback by Patrick Rudolph · 8 years ago
  42. 7123e2e nb/amd/mct_ddr3: Fix revision mask for DR processors by Timothy Pearson · 8 years ago
  43. b3ddf83 nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage by Timothy Pearson · 8 years ago
  44. c00f4d6 nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs by Timothy Pearson · 8 years ago
  45. c094d99 nb/amd/mct_ddr3: Disable MCE framework during DRAM training by Timothy Pearson · 8 years ago
  46. f961bec nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed by Timothy Pearson · 8 years ago
  47. 33aaa92 northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity) by Damien Zammit · 9 years ago
  48. 27e085a nb/intel/sandybridge/raminit: move ram training into seperate function by Patrick Rudolph · 8 years ago
  49. 735ecce nb/intel/sandybridge/raminit: move dimm_info into ramctr_timing by Patrick Rudolph · 8 years ago
  50. e2e0057 nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D() by Timothy Pearson · 8 years ago
  51. ec38c3d nb/amd/amdmct: Select max_lanes based on ECC presence or absence by Damien Zammit · 9 years ago
  52. 54accfe nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values by Timothy Pearson · 8 years ago
  53. f1d807c nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_SW_Fam15() by Timothy Pearson · 8 years ago
  54. f7d4f73 nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set by Timothy Pearson · 8 years ago
  55. 264bf0b cpu/x86/mtrr: move cache_ramstage() to its only user by Aaron Durbin · 8 years ago
  56. bc5ad10 nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training by Timothy Pearson · 8 years ago
  57. 2510e2a northbridge/intel/i3100: Unify UDELAY selection by Stefan Reinauer · 9 years ago
  58. e3fd63f northbridge/intel/i82810: Unify UDELAY selection by Stefan Reinauer · 9 years ago
  59. 63db614 northbridge/intel/i82830: Unify UDELAY selection by Stefan Reinauer · 9 years ago
  60. 2d987fe nb/amd/mct_ddr3: Consolidate duplicated code by Timothy Pearson · 8 years ago
  61. 92fc072 northbridge/intel: move mrccache.c of sandybridge + haswell to common by Alexander Couzens · 8 years ago
  62. 81c5c76 northbridge/intel: move mrc_cache definition into a common header by Alexander Couzens · 8 years ago
  63. f0ab23c nortbridge/sandybridge/mrccache: parse the return code of flash->write by Alexander Couzens · 8 years ago
  64. 10d6fce nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15 by Timothy Pearson · 8 years ago
  65. ed85f61 nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetch by Timothy Pearson · 9 years ago
  66. 2e1f731 nb/amd/mct_ddr3: Require minumum training quality for both read and write by Timothy Pearson · 8 years ago
  67. 50583f0 nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency by Timothy Pearson · 8 years ago
  68. 8eb221d nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks by Timothy Pearson · 8 years ago
  69. bbfcf62 nb/amd/mct_ddr3: Restore previous DQS delay values on failed loop by Timothy Pearson · 8 years ago
  70. c7a1a3e northbridge/i945/gma: Re-enable NVRAM tft_brightness by Alexander Couzens · 8 years ago
  71. 3d840d0 northbridge/intel/i440bx: Unify UDELAY selection by Stefan Reinauer · 9 years ago
  72. 0819a47 northbridge/intel/gm45: Use TSC for ramstage timer per default by Stefan Reinauer · 8 years ago
  73. 8e7928a sandybridge/gma_lvds: support both Sandy&Ivy on one board by Iru Cai · 9 years ago
  74. b97009e nb/intel/sandybridge/raminit: Fill SMBIOS type17 info by Patrick Rudolph · 9 years ago
  75. 9f3f915 nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk by Patrick Rudolph · 9 years ago
  76. 77e45d3 nb/intel/sandybridge/raminit: Make discover_timC_write non cyclic by Patrick Rudolph · 9 years ago
  77. d7ee9dd northbridge/intel: add missing #include guards by Iru Cai · 9 years ago
  78. d912f1d nb/intel/sandybridge/raminit: Adjust timB to prevent overflow by Patrick Rudolph · 9 years ago
  79. 0e92bb0 tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))" by Denis 'GNUtoo' Carikli · 9 years ago
  80. bd1fdc6 nb/intel/sandybridge/raminit: Add XMP support by Patrick Rudolph · 9 years ago
  81. 41462bd nb/amd/amdmct: Add socket specific configuration for FM2 by Damien Zammit · 9 years ago
  82. a649a54 nb/intel/sandybridge/raminit: Improve logging by Patrick Rudolph · 9 years ago
  83. e4f9d5c nb/intel/sandybridge: Start PEG link training by Patrick Rudolph · 9 years ago
  84. e8e66f4 southbridge/intel/bd82x6x: Use common gpio.c by Patrick Rudolph · 9 years ago
  85. 0188b13 nb/intel/sandybridge/raminit: Add shift offset by Patrick Rudolph · 9 years ago
  86. bd82d18 sandybridge: Always include MRC if not using native RAM init. by Vladimir Serbinenko · 9 years ago
  87. 144eea0 Make MRC vs native a config rather than making a separate chipset for it. by Vladimir Serbinenko · 9 years ago
  88. ffbb3c0 Merge sandy/ivybridge romstage flow for MRC and non-MRC. by Vladimir Serbinenko · 9 years ago
  89. 59ff340 Kconfig: Move defaults for CBFS_SIZE by Martin Roth · 9 years ago
  90. b2eea81 sandybridge: Set all native gfx-related options in northbridge code. by Vladimir Serbinenko · 9 years ago
  91. 609bd94 ivy: Add a possiblity for mainboard early init. by Vladimir Serbinenko · 9 years ago
  92. 2dc15e9 Revert "northbridge/intel/peg: Disable unused ports" by Nico Huber · 9 years ago
  93. fec8872 nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h by Timothy Pearson · 9 years ago
  94. 3168236 nb/amd/mct_ddr3: Work around RDIMM training failure by Timothy Pearson · 9 years ago
  95. 0e06f5b northbridge/intel/peg: Disable unused ports by Patrick Rudolph · 9 years ago
  96. a1c3bed nb/intel/sandybridge/raminit: Fix two dimms per channel by Patrick Rudolph · 9 years ago
  97. 2f91403 src: Fix various spelling and whitespace issues. by Martin Roth · 9 years ago
  98. b410d26 nb/amd/amdmct/mct_ddr3: Save and restore SkewMemClk for S3 resume by Timothy Pearson · 9 years ago
  99. 448e386 drivers/pc80: Add PS/2 mouse presence detect by Timothy Pearson · 9 years ago
  100. 3141eac Revert "northbridge/intel/sandybridge: Fix random raminit failures" by Vladimir Serbinenko · 9 years ago