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review.coreboot.org / coreboot / b7e692e0162d51c10c55591822ff8a7053f70056 / src / cpu / intel
  1. 7129ccb cpu/intel/model_6{e,f}x: Unify init files by Paul Menzel · 8 years ago
  2. 996cf79 src/cpu/intel: Add license headers to all files by Martin Roth · 8 years ago
  3. 3f2d6c0 cpu/intel/model_6fx: Add Conroe-L to cpu_device_id list by Arthur Heymans · 8 years ago
  4. ed6fe2f cpu/intel/common: Add/Use common function to set virtualization by Matt DeVillier · 8 years ago
  5. c86c6b3 intel cache-as-ram: Move DCACHE_RAM_BASE by Kyösti Mälkki · 8 years ago
  6. 823020d intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup by Kyösti Mälkki · 8 years ago
  7. 3b3a284 cpu/intel/lga775: Do not select model_6ex CPU by Arthur Heymans · 8 years ago
  8. b84c833 intel/sandybridge: Use postcar_frame for MTRR setup by Kyösti Mälkki · 8 years ago
  9. 140087f CPU: Declare cpu_phys_address_size() for all arch by Kyösti Mälkki · 8 years ago
  10. 77e1399 romstage_handoff: remove code duplication by Aaron Durbin · 8 years ago
  11. c13d65c intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINIT by Kyösti Mälkki · 8 years ago
  12. dfb2de8 intel car: Move pre-ram stack guard lower by Kyösti Mälkki · 8 years ago
  13. bfca670 intel/sandybridge post-car: Redo MTRR settings and stack selection by Kyösti Mälkki · 8 years ago
  14. de01136 intel post-car: Increase stacktop alignment by Kyösti Mälkki · 8 years ago
  15. 39915bc intel cache-as-ram: Unify stack setup by Kyösti Mälkki · 8 years ago
  16. a4ffe9d intel post-car: Separate files for setup_stack_and_mtrrs() by Kyösti Mälkki · 8 years ago
  17. 9b99152 intel/sandybridge: Use common ACPI S3 recovery by Kyösti Mälkki · 8 years ago
  18. c5d972d Move select UDELAY_LAPIC from nb/gm45/Kconfig to cpu/model_1067x/Kconfig by Arthur Heymans · 8 years ago
  19. 306521b cpu/intel/socket_mPGA478MN: Add socket P by Arthur Heymans · 8 years ago
  20. 8160a2f intel post-car: Split legacy sockets by Kyösti Mälkki · 8 years ago
  21. 8cd723b lib/prog_loaders: use common ramstage_cache_invalid() by Aaron Durbin · 8 years ago
  22. 6f8b7df cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZE by Nico Huber · 8 years ago
  23. aacd548 cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4E by Arthur Heymans · 8 years ago
  24. 3eb65ec Kconfig: Add option for microcode filenames by Martin Roth · 8 years ago
  25. 2765a89 src/cpu: Improve code formatting by Elyes HAOUAS · 8 years ago
  26. cbe7464c src/cpu: Add required space before opening parenthesis '(' by Elyes HAOUAS · 8 years ago
  27. 7c8d74c src/cpu: Remove unnecessary whitespace before "\n" by Elyes HAOUAS · 8 years ago
  28. d6e9686 src/cpu: Capitalize CPU, APIC and IOAPIC typo fix by Elyes HAOUAS · 8 years ago
  29. 0cd338e Remove non-ascii & unprintable characters by Martin Roth · 8 years ago
  30. d82be92 src/cpu: Capitalize CPU by Elyes HAOUAS · 8 years ago
  31. 585d1a0 src/cpu: Capitalize ROM and RAM by Elyes HAOUAS · 8 years ago
  32. dc4820b intel car: Use MTRR WRPROT type for XIP cache by Kyösti Mälkki · 8 years ago
  33. 9551bed intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE by Kyösti Mälkki · 8 years ago
  34. e9a9c6a intel/haswell: Remove useless MTRR clear by Kyösti Mälkki · 8 years ago
  35. 3f22abb intel/haswell post-car: Minor fix on MTRR setting by Kyösti Mälkki · 8 years ago
  36. b37d01d3 intel/haswell: Add asmlinkage for romstage_after_car() by Kyösti Mälkki · 8 years ago
  37. 8a2f167 intel car: Unify postcodes by Kyösti Mälkki · 8 years ago
  38. eb61ea8 intel car: Unify whitespace and comment fixes by Kyösti Mälkki · 8 years ago
  39. 9ec6914 intel car: Remove guard on XIP_ROM_SIZE by Kyösti Mälkki · 8 years ago
  40. a27fba6 intel model_106cx: Include CAR from socket directory by Kyösti Mälkki · 8 years ago
  41. e5c00a5 intel post-car: Consolidate choose_top_of_stack() by Kyösti Mälkki · 8 years ago
  42. 1891bfd intel/haswell: No need for ACPI S3 resume backup by Kyösti Mälkki · 8 years ago
  43. 65e8f64 intel romstage: Use run_ramstage() by Kyösti Mälkki · 8 years ago
  44. cf0e60f ACPI S3: Add common recovery code by Kyösti Mälkki · 8 years ago
  45. 65cc526 Ignore RAMTOP for MTRRs by Kyösti Mälkki · 8 years ago
  46. 75d139b intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP by Kyösti Mälkki · 8 years ago
  47. 8431fcb intel/model_2065x: Prepare for dynamic CONFIG_RAMTOP by Kyösti Mälkki · 8 years ago
  48. b4f827d intel cache-as-ram: Fix comment about MTRRs by Kyösti Mälkki · 8 years ago
  49. 15fa992 intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP by Kyösti Mälkki · 8 years ago
  50. 408d392 intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP by Kyösti Mälkki · 8 years ago
  51. 07921540d intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP by Kyösti Mälkki · 8 years ago
  52. e325b22 intel: Fix romstage main() with asmlinkage by Kyösti Mälkki · 8 years ago
  53. 831a7ef intel/cache_as_ram_ht.inc: Fix include by Kyösti Mälkki · 8 years ago
  54. 9d2762c intel cache_as_ram: Fix typo in comment by Kyösti Mälkki · 8 years ago
  55. d72cc41 intel/model_206ax: Move platform specific defines by Kyösti Mälkki · 8 years ago
  56. a969ed3 Move definitions of HIGH_MEMORY_SAVE by Kyösti Mälkki · 8 years ago
  57. 465eff6 Fix some cbmem.h includes by Kyösti Mälkki · 8 years ago
  58. 6366d92 {cpu,soc}/intel: remove unused smm_init() function by Aaron Durbin · 8 years ago
  59. 463af33 cpu/intel/haswell: convert to using common MP and SMM init by Aaron Durbin · 8 years ago
  60. d87c7bc cpu/x86: remove BACKUP_DEFAULT_SMM_REGION option by Aaron Durbin · 8 years ago
  61. 0e55632 cpu/x86/mp_init: remove unused callback arguments by Aaron Durbin · 8 years ago
  62. 3d840d0 northbridge/intel/i440bx: Unify UDELAY selection by Stefan Reinauer · 9 years ago
  63. 2a08137 x86 chipsets: utilize x86_setup_mtrrs_with_detect() by Aaron Durbin · 8 years ago
  64. 0e92bb0 tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))" by Denis 'GNUtoo' Carikli · 9 years ago
  65. 07a196e CPU/intel: Add missing license headers by Damien Roth · 9 years ago
  66. 144eea0 Make MRC vs native a config rather than making a separate chipset for it. by Vladimir Serbinenko · 9 years ago
  67. a02bb65 cpu/intel/microcode: allow microcode to be loaded in romstage by Aaron Durbin · 9 years ago
  68. 7c38e1e8 Remove #ifdef checks on Kconfig symbols by Martin Roth · 9 years ago
  69. ea7b636 fsp_model_406dx: use external microcode .h files for rangeley by Martin Roth · 9 years ago
  70. 149c4c5 x86/smm: Initialize SMM on some CPUs one-by-one by Damien Zammit · 9 years ago
  71. 0cf0805 cpu/intel/socket_FCBGA559: Add new socket for Atom D5xx by Damien Zammit · 9 years ago
  72. 5cf5828 fsp1_0: Remove hardcoded microcode locations by Martin Roth · 9 years ago
  73. d35c264 intel/fsp_model_406dx: Load APs microcode in model_406dx_init by David Guckian · 9 years ago
  74. 5f06d53 intel/fsp_rangeley: Load BSP microcode in bootblock by David Guckian · 9 years ago
  75. 2d72345 cpu/intel: Add socket BGA1284 by Marc Jones · 9 years ago
  76. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  77. 0ace013 sandybridge: Disable parallel CPU initialization by Nico Huber · 9 years ago
  78. 158d001 cpu/intel/fsp_model_206ax: Load microcode in coreboot by Martin Roth · 9 years ago
  79. 469f593 cpu/intel: Move Power notification ASL code into `common/acpi` by Paul Menzel · 9 years ago
  80. bf6b83a Revert "Remove sandybridge and ivybridge FSP code path" by Martin Roth · 9 years ago
  81. 86091f9 cpu/mtrr.h: Fix macro names for MTRR registers by Alexandru Gagniuc · 9 years ago
  82. 5856240 Revert "Remove FSP Rangeley SOC and mohonpeak board support" by Martin Roth · 9 years ago
  83. ee2740b arch/x86/bootblock: Do not include non-code files in bootblock.S by Alexandru Gagniuc · 9 years ago
  84. 72bb66e x86/bootblock: Use LDFLAGS_bootblock to enable garbage collection by Alexandru Gagniuc · 9 years ago
  85. 959478a Remove FSP Rangeley SOC and mohonpeak board support by Alexandru Gagniuc · 9 years ago
  86. fb50124 Remove sandybridge and ivybridge FSP code path by Alexandru Gagniuc · 9 years ago
  87. ecf2eb4 sandybridge ivybridge: Treat native init as first class citizen by Alexandru Gagniuc · 9 years ago
  88. 1d85700 cpu: microcode: Use microcode stored in binary format by Alexandru Gagniuc · 9 years ago
  89. 9796f60 coreboot: move TS_END_ROMSTAGE to one spot by Aaron Durbin · 9 years ago
  90. 0f045a6 intel/model_2065x/Kconfig: Don't use LAPIC_MONOTONIC_TIMER by Martin Roth · 9 years ago
  91. 439356f x86: remove cpu_incs as romstage Make variable by Aaron Durbin · 9 years ago
  92. df20506 Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig by Martin Roth · 9 years ago
  93. 30b755b Add SoC specific microcode update check in ramstage by Rizwan Qureshi · 9 years ago
  94. 4a45ec4 x86: Drop -Wa,--divide by Stefan Reinauer · 9 years ago
  95. 0f9aa1c model_2065x: Use common i945-ivy TSEG SMM init. by Vladimir Serbinenko · 9 years ago
  96. efc01f0 model_206ax: Fix APIC map when HT is disabled. by Vladimir Serbinenko · 9 years ago
  97. f34082c fsp_model_206ax: Use common i945-ivy tseg SMM init. by Vladimir Serbinenko · 9 years ago
  98. 42e6856 stage_cache: use cbmem init hooks by Aaron Durbin · 9 years ago
  99. c16e9dfa Create i945-ivy smm tseg init based on ivy code. by Vladimir Serbinenko · 9 years ago
  100. 5264862 Remove empty lines at end of file by Elyes HAOUAS · 9 years ago