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review.coreboot.org / coreboot / a9a2e10eed693f1e0e60ea72c269125d3fadcb8a / src / southbridge / amd / sr5650
  1. a9a2e10 southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop by Edward O'Callaghan · 10 years ago
  2. 0f92f63 Uniformly spell frequency unit symbol as Hz by Elyes HAOUAS · 10 years ago
  3. 6a12109 AMD RS780, SR5650: PcieTrainPort: Fix typo *i*gnoring in comment by Paul Menzel · 11 years ago
  4. 24d1d4b x86: Unify arch/io.h and arch/romcc_io.h by Stefan Reinauer · 11 years ago
  5. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  6. 23f38cd Get rid of drivers class by Patrick Georgi · 12 years ago
  7. 8ada152 Unify use of bool config variables by Stefan Reinauer · 12 years ago
  8. fee73df Auto-declare chip_operations by Kyösti Mälkki · 12 years ago
  9. f8f0062 Some more #if cleanup by Patrick Georgi · 12 years ago
  10. da52aed Fixes Fam10/SR5650 cpu not recognized message. by Dave Frodin · 13 years ago
  11. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 13 years ago
  12. af3dce9 Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c. by Stefan Reinauer · 13 years ago
  13. 00c8c4a Update AMD SR5650 and SB700 by efdesign98 · 13 years ago
  14. 98fcc09 Add AMD SR56x0 support. by Zheng Bao · 13 years ago