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review.coreboot.org / coreboot / a46a712610c130cdadfe1ebf6bec9ad22e474dac / src / southbridge
  1. 51cb26d SMM: Fix state save map for sandybridge and TSEG by Duncan Laurie · 12 years ago
  2. 181bbdd SMM: Add option for SPI driver to be available in SMM by Duncan Laurie · 12 years ago
  3. 9842ad8 Fix automatic ME detection in finalize by Stefan Reinauer · 12 years ago
  4. 998f3a2 Cougar/Panther Point: Compile in ME7 and ME8 code at the same time by Stefan Reinauer · 12 years ago
  5. 49058c0 Fix ME hash functions on Panther Point/Cougar Point by Stefan Reinauer · 12 years ago
  6. ef6b08c Add PCIe port disable debug message by Marc Jones · 12 years ago
  7. 9d3e832 bd82x6x: Support power-on-after-power-fail better by Stefan Reinauer · 12 years ago
  8. 8bdbddf Fix function generating GPIO state based vector by Vadim Bendebury · 12 years ago
  9. 3f6a4d7 Add specific power management init code for PantherPoint by Duncan Laurie · 12 years ago
  10. 8e515d3 RTC: Enable extended CMOS in the bootblock by Duncan Laurie · 12 years ago
  11. 9a380ab bd82x6x: Convert all PCI ID lists to new scheme by Stefan Reinauer · 12 years ago
  12. baae2d2 Add support for HM70 and NM70 LPC bridge by Stefan Reinauer · 12 years ago
  13. b5dfcae cs5536: add smbus support in ramstage by Christian Gmeiner · 12 years ago
  14. 5f3aca3 SPI flash layer: remove unused function spi_flash_free() by Stefan Reinauer · 12 years ago
  15. 6db7f34 Trinity wrapper code improvement. by zbao · 12 years ago
  16. cc55b9b Define global uma_memory variables by Kyösti Mälkki · 12 years ago
  17. 246e84b AGESA F15 wrapper for Hudson. by zbao · 12 years ago
  18. 87ed617 Fix AMD S3 block generator on Cygwin by Patrick Georgi · 12 years ago
  19. 2c08f6a AGESA F15 wrapper for Trinity by zbao · 12 years ago
  20. 1f20da7 i3100: add smbus_write_byte() by Sven Schnelle · 12 years ago
  21. dab6bfe i3100: Enable second IOAPIC for PCI-X by Sven Schnelle · 12 years ago
  22. 904a0ec Don't use 64-bit constant 0x100000000 in linker scripts by Nico Huber · 12 years ago
  23. 9aa4389 Update SB800 CIMX FADT by Martin Roth · 12 years ago
  24. 3b3a1a1 Provide functions to access arbitrary GPIO pins and vectors by Vadim Bendebury · 12 years ago
  25. 691c9f0 Add support for Panther Point to SPI driver by Stefan Reinauer · 12 years ago
  26. 14b23a6 Fix compilation with CONFIG_DEBUG_SPI_FLASH enabled by Stefan Reinauer · 12 years ago
  27. 71695d8 Fix full reset for Ivy Bridge platforms by Vadim Bendebury · 12 years ago
  28. 2f00ce3 cbtypes.h: Unify cbtypes.h used in AMD board's code by Vikram Narayanan · 12 years ago
  29. ba3711c Fix fadt legacy free setting. by Marc Jones · 12 years ago
  30. 7c9ef4f Add legacy free setting and override to fadt.c by Marc Jones · 12 years ago
  31. b547c4f Merge sb800 fadt fixes from South Station mainboard to southbridge fadt. by Marc Jones · 12 years ago
  32. 1c56d9b Add SPI flash driver by Stefan Reinauer · 12 years ago
  33. 923d200 Unmark source files as executables by Alec Ari · 12 years ago
  34. 76cfcbc Move fadt.c to the cimx sb800 southbridge directory to be shared. by Marc Jones · 12 years ago
  35. 7b860ed Add simple PMIO & PMIO2 read/write routines to CIMX wrapper by Martin Roth · 12 years ago
  36. f8f0062 Some more #if cleanup by Patrick Georgi · 12 years ago
  37. e166782 Clean up #ifs by Patrick Georgi · 12 years ago
  38. 4aca5d7 Fix issue with PCIe power management setup by Duncan Laurie · 12 years ago
  39. b9fe01c Add an option to enable PCIe root port coalescing by Duncan Laurie · 12 years ago
  40. c323036 Update PCIe Root Port _PRT to handle re-mapped functions by Duncan Laurie · 12 years ago
  41. 816d081 Fix SATA port map to only enable port 0 by Stefan Reinauer · 12 years ago
  42. 95be1d6 Don't disable ACPI in the S3 resume path by Duncan Laurie · 12 years ago
  43. 459b777 add new LPC controller device ID value by Vadim Bendebury · 12 years ago
  44. 8049fc9 Allow device ID arrays in the PCI driver structure by Vadim Bendebury · 12 years ago
  45. 80529ab Cougar Point southbridge: Add includes and drop post_code() by Stefan Reinauer · 12 years ago
  46. bf34e94 SMM: unify mainboard APM command handlers by Stefan Reinauer · 12 years ago
  47. 1d89f14 Intel 82801dx: compile early_smbus as separate object by Kyösti Mälkki · 12 years ago
  48. 26b00e6 Refactor some alignment handling by Patrick Georgi · 12 years ago
  49. a20132b Do not produce temp s3.rom if the board doesn't need it. by zbao · 12 years ago
  50. e380b0f More portable s3 scratch space creation by Patrick Georgi · 12 years ago
  51. 9bcdbf8 Add Southbridge support for S3. by zbao · 12 years ago
  52. 2c2e78d Unify IO APIC address specification by Patrick Georgi · 12 years ago
  53. 8e07382 Add support for Intel Panther Point PCH by Stefan Reinauer · 12 years ago
  54. 01bd79f Add sb800 spi support. by zbao · 12 years ago
  55. 6b89b4c Add support for RDC R8610 Southbridge by Rudolf Marek · 12 years ago
  56. 8a85bcc i82801gx: Support power-on-after-power-fail better by Patrick Georgi · 13 years ago
  57. c07466b i82801gx: Use CMOS variable if available for power-on on power failure by Patrick Georgi · 13 years ago
  58. 35e1c86 VIA southbridge K8T890: Apply un-written naming rules by Kyösti Mälkki · 12 years ago
  59. c5fc7db Move C labels to start-of-line by Patrick Georgi · 12 years ago
  60. 399fcdd AMD southbridge: remove sp5100 by Kyösti Mälkki · 12 years ago
  61. b05bf5b amd/sb600: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  62. c877d22 Force SB600 bootblock to use I/O for PCI config by Dave Frodin · 13 years ago
  63. 5257c27 Force SB700 bootblock code to use I/O for PCI config cycles. by Dave Frodin · 13 years ago
  64. 2eacc0e Force SB800 bootblock to use I/O for PCI config by Dave Frodin · 13 years ago
  65. da52aed Fixes Fam10/SR5650 cpu not recognized message. by Dave Frodin · 13 years ago
  66. a22f78b nvidia/mcp55: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  67. 0e992be amd/sb700: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  68. c46f450 intel/i82801cx: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  69. e0ddbc7 sis/sis966: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  70. 7389378 intel/i82801ex: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  71. 62246f7 intel/sch: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  72. 024d8d9 amd/sb800: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  73. 334328a Avoid ../../.. paths in ASL files by Patrick Georgi · 12 years ago
  74. 472efa6 Remove whitespace. by Patrick Georgi · 12 years ago
  75. 152738f amd/amd8111: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  76. a842aec intel/82801dx: Move HAVE_HARD_RESET to southbridge by Patrick Georgi · 12 years ago
  77. 131c936 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper by Kerry Sheh · 12 years ago
  78. b06bd8d i3100: configure pci irqs by Sven Schnelle · 13 years ago
  79. 56f2a6d CIMX wrapper: remove redudant traversing sb800 and sb900 CIMX dir by Kerry Sheh · 13 years ago
  80. f61ad93 i3100: add sata_ports_implemented option by Sven Schnelle · 13 years ago
  81. ab46c15 i3100: Add init sequence by Sven Schnelle · 13 years ago
  82. 0f1dc4e Add subsystem callbacks for VT8237x and VT890 family of chipsets by Rudolf Marek · 13 years ago
  83. a31bb07 Unify ID_SECTION_OFFSET and mark it deprecated by Patrick Georgi · 13 years ago
  84. 75fb40e Add missing HAVE_HARD_RESET by Sven Schnelle · 13 years ago
  85. b5d81eb rs780: correct comment in switching_gpp_configurations() by Jonathan A. Kollasch · 13 years ago
  86. f3fe3d2 rs780: use bitwise rather than boolean not by Jonathan A. Kollasch · 13 years ago
  87. 8bd41cd rs780: power down GPPSB SB lane pads in correct PCIe core by Jonathan A. Kollasch · 13 years ago
  88. f154c01 Persimmon audio codec verb patch. by Marc Jones · 13 years ago
  89. 4c132bb Fix AMD 8132 and 8151 southbridge builds by Kyösti Mälkki · 13 years ago
  90. 7519d77 RS780: print the vgainfo by Denis 'GNUtoo' Carikli · 13 years ago
  91. b532057 make GPIOs and misc configurable via devicetree by Florian Zumbiehl · 13 years ago
  92. 98236ca make INT[EFGH]# of vt8237 configurable as gpio via devicetree by Florian Zumbiehl · 13 years ago
  93. 6a3e8d6 some black magic for initializing the old version of the k8t800 by Florian Zumbiehl · 13 years ago
  94. 1b940fd implement usb2 termination and dpll delay setting for vt8237r by Florian Zumbiehl · 13 years ago
  95. 28bdd8d i3100: Add HAVE_HARD_RESET by Sven Schnelle · 13 years ago
  96. 912d891 vt8237: add support for setting the power state after loss of power by Florian Zumbiehl · 13 years ago
  97. 50dadfb compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD by Florian Zumbiehl · 13 years ago
  98. be7d8dc support for different location of HT registers in old version of K8T800 by Florian Zumbiehl · 13 years ago
  99. 2e2b84e move function from header file to .c file by Stefan Reinauer · 13 years ago
  100. 0802ad9 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible by Florian Zumbiehl · 13 years ago