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review.coreboot.org / coreboot / 9631016660423d0585a1 / src / soc / nvidia / tegra132 / ramstage.c
  1. 7dcf9d5 arm64: tegra132: tegra210: Remove old arm64/stage_entry.S by Julius Werner · 9 years ago
  2. fdb3a8d arm64: Remove cpu intialization through device-tree by Furquan Shaikh · 9 years ago
  3. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  4. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  5. 96195ee tegra132: Change all SoC headers to <soc/headername.h> system by Julius Werner · 10 years ago
  6. aa228d0 Tegra132: Configure CPU clock by Jimmy Zhang · 10 years ago
  7. 7ddb5f7 tegra132: Add Trust Zone register access by Aaron Durbin · 10 years ago
  8. da9b9f3 t132: Add mmu support by Furquan Shaikh · 10 years ago
  9. b397f01 tegra132: split memory range querying to above/below 4GiB by Aaron Durbin · 10 years ago
  10. bc3019c t132: handle optional Trust Zone region correctly by Aaron Durbin · 10 years ago