Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 9631016660423d0585a1 / src / soc / intel / fsp_baytrail / ramstage.c
  1. fa6014a intel/fsp_baytrail: rename include folder baytrail to include/soc by Ben Gardner · 9 years ago
  2. 2d3d1b7 baytrail: add C0 and D0 stepping decode by Ben Gardner · 9 years ago
  3. 72e33a7 intel/fsp_baytrail: Load APs microcode in baytrail_init_cpus by York Yang · 9 years ago
  4. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  5. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  6. 9e94dbf ACPI: Get S3 resume state from romstage_handoff by Kyösti Mälkki · 10 years ago
  7. ed0c838 intel/fsp_baytrail: Add S3 suspend/resume Support by Mohan D'Costa · 10 years ago
  8. 433659a fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip by Martin Roth · 10 years ago