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review.coreboot.org / coreboot / 9631016660423d0585a1 / src / cpu / amd / agesa
  1. 030902b AGESA: skip s3_resume.h if CONFIG_HAVE_ACPI_RESUME is disabled by Jens Rottmann · 11 years ago
  2. 502533f Revert "AMD S3: Program the flash in a bigger data packet" by Dave Frodin · 11 years ago
  3. 22ec9f9 AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE' by Zheng Bao · 12 years ago
  4. f57d0dc AMD S3: Change S3_VOLATILE_POS to S3_DATA_POS by Zheng Bao · 12 years ago
  5. ca6e1f6 AMD S3: Program the flash in a bigger data packet by Zheng Bao · 12 years ago
  6. 96508a7 AMD S3: Include the s3_resume.h only when S3 is enabled. by Zheng Bao · 12 years ago
  7. 600784e spi.h: Rename the spi.h to spi-generic.h by Zheng Bao · 12 years ago
  8. c52e106 AMD S3: Add missing erasing flash sector for saving MTRR register by Zheng Bao · 12 years ago
  9. e07e253 AMD S3: Change the hardcoded data size to macros. by Zheng Bao · 12 years ago
  10. 336b8b1 AGESA: Kconfig: Drop useless depends statement by Patrick Georgi · 12 years ago
  11. 105da50 AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITS by Zheng Bao · 12 years ago
  12. 3316cf2 Claim the SPI bus before writes if the IMC ROM is present by Martin Roth · 12 years ago
  13. 7bcffa5 AMD S3: Leverage the public SPI routine by Zheng Bao · 12 years ago
  14. e135ac5 Remove AMD special case for LAPIC based udelay() by Patrick Georgi · 12 years ago
  15. 23f38cd Get rid of drivers class by Patrick Georgi · 12 years ago
  16. 8ada152 Unify use of bool config variables by Stefan Reinauer · 12 years ago
  17. 40f36e0 Make sure only one udelay function is available by Stefan Reinauer · 12 years ago
  18. f3b86b3 AMD agesa: add enable cache at the end of disable_cache_as_ram by Siyuan Wang · 12 years ago
  19. 0279036 Remove chip.h files without config structure by Kyösti Mälkki · 12 years ago
  20. fee73df Auto-declare chip_operations by Kyösti Mälkki · 12 years ago
  21. 0db6820 Synchronize rdtsc instructions by Stefan Reinauer · 12 years ago
  22. f85398c AMD S3: Remove the hardcoded volatile position by zbao · 12 years ago
  23. 57879c9 Make the device tree available in the rom stage by Stefan Reinauer · 12 years ago
  24. 22b7a55 Remove useless file from building. by zbao · 12 years ago
  25. 2c08f6a AGESA F15 wrapper for Trinity by zbao · 12 years ago
  26. e166782 Clean up #ifs by Patrick Georgi · 12 years ago
  27. 05e740f Replace cache control magic numbers with symbols by Patrick Georgi · 12 years ago
  28. 1e6bf09 amd: Fix unused variable warning by Vikram Narayanan · 12 years ago
  29. f722373 S3 code in coreboot public folder. by zbao · 12 years ago
  30. 3925622 S3 code in vendorcode folder. by zbao · 12 years ago
  31. afd141d S3 code whitespaces changes. by zbao · 12 years ago
  32. d11ca1d Rename AMD_AGESA to CPU_AMD_AGESA by Kyösti Mälkki · 12 years ago
  33. f5bb477 Fix AMD Agesa leaking Kconfig by Kyösti Mälkki · 12 years ago
  34. 472efa6 Remove whitespace. by Patrick Georgi · 13 years ago
  35. d3e990c AGESA F15: AGESA family15 model 00-0fh cpu wrapper by Kerry Sheh · 13 years ago
  36. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 13 years ago
  37. 784544b Remove XIP_ROM_BASE by Patrick Georgi · 13 years ago
  38. f73535c AMD F14 Rev C0 update by Kerry She · 13 years ago
  39. 84cbce2 Update AMD F14 Agesa to support Rev C0 cpus by efdesign98 · 13 years ago
  40. 4b50834 Add AMD Family 10 support to cpu folder by efdesign98 · 13 years ago
  41. 7c0c64e Addition of Family12/SB900 wrapper code by efdesign98 · 13 years ago
  42. 621ca38 Move existing AMD Ffamily14 code to f14 folder by efdesign98 · 13 years ago
  43. 05a89ab Rename {CPU|NB|SB}/amd/*_wrapper folders by efdesign98 · 13 years ago