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northbridge
9551bed
intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
by Kyösti Mälkki
· 8 years ago
b921725
nb/intel/x4x: Fix CAS latency detection
by Damien Zammit
· 8 years ago
df6eb79
intel/x4x: Do not use scratchpad register for ACPI S3
by Kyösti Mälkki
· 8 years ago
32a38ee
intel/pineview: Do not use scratchpad register for ACPI S3
by Kyösti Mälkki
· 8 years ago
bce9bbd
AGESA: Use common romstage ram stack
by Kyösti Mälkki
· 8 years ago
4dc680a
nb/intel/pineview/northbridge.c: Remove legacy_hole_size_k declaration
by Jonathan Neuschäfer
· 8 years ago
9ae0985
nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM
by Damien Zammit
· 8 years ago
e4da9aa
intel/sandybridge: read correct leaf for cpu family
by Ryan Salsamendi
· 8 years ago
e6b5a4f
intel/i945: Use common ACPI S3 recovery
by Kyösti Mälkki
· 8 years ago
0306e6a
intel/sandybridge: Fix builds with System Agent blob
by Kyösti Mälkki
· 8 years ago
65cc526
Ignore RAMTOP for MTRRs
by Kyösti Mälkki
· 8 years ago
75d139b
intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP
by Kyösti Mälkki
· 8 years ago
55409eb
nb/intel/sandybridge/raminit: Use supported CAS
by Patrick Rudolph
· 8 years ago
d4c53e3
nb/intel/sandybridge/raminit: Do code cleanup
by Patrick Rudolph
· 8 years ago
b7b1b28
nb/intel/sandybridge/raminit: Do code cleanup
by Patrick Rudolph
· 8 years ago
7bddd30
nb/intel/sandybridge/raminit: Allow 933Mhz on Lenovo devices
by Patrick Rudolph
· 8 years ago
d72cc41
intel/model_206ax: Move platform specific defines
by Kyösti Mälkki
· 8 years ago
a969ed3
Move definitions of HIGH_MEMORY_SAVE
by Kyösti Mälkki
· 8 years ago
266a1f7
nb/intel/raminit (native): Read PCI mmio size from devicetree
by Patrick Rudolph
· 8 years ago
bb9c90a
nb/intel: Factor out common MRC code
by Patrick Rudolph
· 8 years ago
68e1dcf
nb/intel/x4x: Fix unpopulated value
by Damien Zammit
· 8 years ago
7afcfe0
gm45: enable setting all vram sizes from cmos
by Arthur Heymans
· 8 years ago
5003632
AGESA: Fix invalid use of CFG_ declarations
by Kyösti Mälkki
· 8 years ago
a090ae0
nb/intel/x4x: Add DMI/EP init
by Damien Zammit
· 8 years ago
8f3aaa8
Fix leaking CONFIG_VGA=y
by Kyösti Mälkki
· 8 years ago
4bab6e7
intel/sch: Merge northbridge and southbridge in src/soc
by Stefan Reinauer
· 8 years ago
84da72c
nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structure
by Timothy Pearson
· 8 years ago
d112f46
nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15h
by Timothy Pearson
· 8 years ago
66fbeae
intel/pineview: Don't try to store 34 bits in 32
by Stefan Reinauer
· 8 years ago
617536e
amd/gx2 + amd/lx: Fix shift overflow issue
by Stefan Reinauer
· 8 years ago
3b0f20b
rdc/r8610: Move to src/soc
by Stefan Reinauer
· 8 years ago
5caf89b
dmp/vortex86ex: Merge northbridge and southbridge into soc
by Stefan Reinauer
· 8 years ago
9c9bde3
nb/intel/sandybridge/raminit: support calling dram_freq multiple times
by Patrick Rudolph
· 8 years ago
2ccb74b
nb/intel/sandybridge/raminit: add additional fallbacks
by Patrick Rudolph
· 8 years ago
1e302cb
nb/intel/gm45: Fix native text mode initialization
by Nick High
· 8 years ago
394041b
nb/amd/mct_ddr3: Only initialize ECC bits once
by Timothy Pearson
· 8 years ago
ac6bd5b0
nb/amd/mct_ddr3: Warn if MaxRdLatency training fails on Family 15h
by Timothy Pearson
· 8 years ago
2bb1d30
nb/amd/mct_ddr3: Stop receiver enable cycle training after window found
by Timothy Pearson
· 8 years ago
29dd5da
nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0
by Timothy Pearson
· 8 years ago
263c679
nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4
by Timothy Pearson
· 8 years ago
7f731f8
nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15h
by Timothy Pearson
· 8 years ago
588ccaa
nb/intel/sandybridge/raminit: fix regression "always use mrccache"
by Patrick Rudolph
· 8 years ago
4.4
4.4
09e3bfb
nb/amd/mct_ddr3: Restart system on training failure instead of using die()
by Timothy Pearson
· 8 years ago
0739b9f
nb/amd/mct_ddr3: Report correct DIMM in MRS setup routines
by Timothy Pearson
· 8 years ago
3242bcf
nb/amd/mct_ddr3: Fix a number of minor errors in RDIMM setup
by Timothy Pearson
· 8 years ago
4488d73
nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change
by Timothy Pearson
· 8 years ago
8b9c807
Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"
by Timothy Pearson
· 8 years ago
5a35936
nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change
by Timothy Pearson
· 8 years ago
4901601
nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs
by Timothy Pearson
· 8 years ago
b474afd
nb/amd/mct_ddr3: Run fence training on each node after memory clock change
by Timothy Pearson
· 8 years ago
318e2ac
AMD CIMX: Drop unused code
by Kyösti Mälkki
· 8 years ago
86ddd73
kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme
by Stefan Reinauer
· 8 years ago
5949371
northbridge/amd/{lx,gx2}: remove immediate accesses of 0
by Patrick Georgi
· 8 years ago
46f8bd7
amd/agesa/family12/dimmSpd.c: Indent (tab) fix
by Edward O'Callaghan
· 10 years ago
186b9de
and/nb/mct_ddr3: Pack all structures passed to ramstage and set alignment
by Timothy Pearson
· 8 years ago
54e0551
nb/amd/amdfam10: Write MCT variables to flash after PCI configuration
by Timothy Pearson
· 8 years ago
56abd4d
nb/intel/sandybridge/raminit: always use mrccache
by Patrick Rudolph
· 8 years ago
5a57725
Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed"
by Timothy Pearson
· 8 years ago
ba817d0
nb/amd/mct_ddr3: Reenable sync flood after ECC init
by Timothy Pearson
· 8 years ago
1d9370b
nb/amd/mct_ddr3: Add MCE reporting logic
by Timothy Pearson
· 8 years ago
49e917b
nb/amd/amdfam10: Only flag machine check exception if valid bit is set
by Timothy Pearson
· 8 years ago
c5c3d76
nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform level
by Timothy Pearson
· 8 years ago
31d1959
nb/intel/sandybridge/raminit: die in toplevel function
by Patrick Rudolph
· 8 years ago
24a845b
nb/intel/sandybridge/raminit: prepare raminit for fallback
by Patrick Rudolph
· 8 years ago
7123e2e
nb/amd/mct_ddr3: Fix revision mask for DR processors
by Timothy Pearson
· 8 years ago
b3ddf83
nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
by Timothy Pearson
· 8 years ago
c00f4d6
nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs
by Timothy Pearson
· 8 years ago
c094d99
nb/amd/mct_ddr3: Disable MCE framework during DRAM training
by Timothy Pearson
· 8 years ago
f961bec
nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed
by Timothy Pearson
· 8 years ago
33aaa92
northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity)
by Damien Zammit
· 9 years ago
27e085a
nb/intel/sandybridge/raminit: move ram training into seperate function
by Patrick Rudolph
· 8 years ago
735ecce
nb/intel/sandybridge/raminit: move dimm_info into ramctr_timing
by Patrick Rudolph
· 8 years ago
e2e0057
nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D()
by Timothy Pearson
· 8 years ago
ec38c3d
nb/amd/amdmct: Select max_lanes based on ECC presence or absence
by Damien Zammit
· 9 years ago
54accfe
nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values
by Timothy Pearson
· 8 years ago
f1d807c
nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_SW_Fam15()
by Timothy Pearson
· 8 years ago
f7d4f73
nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set
by Timothy Pearson
· 8 years ago
264bf0b
cpu/x86/mtrr: move cache_ramstage() to its only user
by Aaron Durbin
· 8 years ago
bc5ad10
nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training
by Timothy Pearson
· 8 years ago
2510e2a
northbridge/intel/i3100: Unify UDELAY selection
by Stefan Reinauer
· 8 years ago
e3fd63f
northbridge/intel/i82810: Unify UDELAY selection
by Stefan Reinauer
· 8 years ago
63db614
northbridge/intel/i82830: Unify UDELAY selection
by Stefan Reinauer
· 8 years ago
2d987fe
nb/amd/mct_ddr3: Consolidate duplicated code
by Timothy Pearson
· 8 years ago
92fc072
northbridge/intel: move mrccache.c of sandybridge + haswell to common
by Alexander Couzens
· 8 years ago
81c5c76
northbridge/intel: move mrc_cache definition into a common header
by Alexander Couzens
· 8 years ago
f0ab23c
nortbridge/sandybridge/mrccache: parse the return code of flash->write
by Alexander Couzens
· 8 years ago
10d6fce
nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15
by Timothy Pearson
· 8 years ago
ed85f61
nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetch
by Timothy Pearson
· 8 years ago
2e1f731
nb/amd/mct_ddr3: Require minumum training quality for both read and write
by Timothy Pearson
· 8 years ago
50583f0
nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency
by Timothy Pearson
· 8 years ago
8eb221d
nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks
by Timothy Pearson
· 8 years ago
bbfcf62
nb/amd/mct_ddr3: Restore previous DQS delay values on failed loop
by Timothy Pearson
· 8 years ago
c7a1a3e
northbridge/i945/gma: Re-enable NVRAM tft_brightness
by Alexander Couzens
· 8 years ago
3d840d0
northbridge/intel/i440bx: Unify UDELAY selection
by Stefan Reinauer
· 8 years ago
0819a47
northbridge/intel/gm45: Use TSC for ramstage timer per default
by Stefan Reinauer
· 8 years ago
8e7928a
sandybridge/gma_lvds: support both Sandy&Ivy on one board
by Iru Cai
· 9 years ago
b97009e
nb/intel/sandybridge/raminit: Fill SMBIOS type17 info
by Patrick Rudolph
· 8 years ago
9f3f915
nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk
by Patrick Rudolph
· 9 years ago
77e45d3
nb/intel/sandybridge/raminit: Make discover_timC_write non cyclic
by Patrick Rudolph
· 8 years ago
d7ee9dd
northbridge/intel: add missing #include guards
by Iru Cai
· 8 years ago
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