- 8508cff Update Ivybridge GT power meter tables by Duncan Laurie · 12 years ago
- dd585b8 Update ivybridge graphics initialization by Duncan Laurie · 12 years ago
- 7b508dd Only send ME Dram Init Done message on Sandybridge by Duncan Laurie · 12 years ago
- 0ff99b7 Modify DMI init for IvyBridge by Vincent Palatin · 12 years ago
- e6063fe Fix Sandybridge/Ivybridge mainboards according to code review by Stefan Reinauer · 12 years ago
- 6ea86b1 Sandybridge: Temporarily disable MRC cache finding code by Stefan Reinauer · 12 years ago
- a403c68 Add default map_oprom_vendev() for AMD Family 14h processors. by Martin Roth · 12 years ago
- e9dfdd9 Reverse Vendor ID & Device ID for map_oprom_vendev() by Martin Roth · 12 years ago
- 16401b8 SMM: Add udelay on Sandybridge systems by Stefan Reinauer · 12 years ago
- 93b4ed9 Intel e7505: build as separate object file by Kyösti Mälkki · 12 years ago
- 97c064f Intel e7505: enable ECC scrubbing by Kyösti Mälkki · 12 years ago
- 26b00e6 Refactor some alignment handling by Patrick Georgi · 12 years ago
- 77e4f7d Intel e7505: refactor only by Kyösti Mälkki · 12 years ago
- 26c7b86 Intel e7505: handlers for undocumented registers by Kyösti Mälkki · 12 years ago
- f722373 S3 code in coreboot public folder. by zbao · 12 years ago
- 2c2e78d Unify IO APIC address specification by Patrick Georgi · 13 years ago
- 5c1ff92 Intel e7505: cleanups by Kyösti Mälkki · 12 years ago
- 5bd271b Intel e7505: renames only by Kyösti Mälkki · 12 years ago
- cab72d9 amdfam10: add phenom II as known cpu by Bernhard Urban · 12 years ago
- 00636b0 Add support for Intel Sandybridge CPU (northbridge part) by Stefan Reinauer · 12 years ago
- c0c5ac7 Add the support for RDC R8610 Northbridge by Rudolf Marek · 12 years ago
- dd3b227 Fix AMD Fam15 CBMEM allocation by Stefan Reinauer · 12 years ago
- 30b46ce Fix AMD Fam12 CBMEM allocation by Stefan Reinauer · 12 years ago
- cc6c615 Fix AMD Fam10 CBMEM allocation by Stefan Reinauer · 12 years ago
- 3ae1c65 AMD Agesa: delete no-op bootblock files by Kyösti Mälkki · 12 years ago
- d11ca1d Rename AMD_AGESA to CPU_AMD_AGESA by Kyösti Mälkki · 12 years ago
- f5bb477 Fix AMD Agesa leaking Kconfig by Kyösti Mälkki · 12 years ago
- eb5e28f Intel northbridge I945: Apply un-written naming rules by Kyösti Mälkki · 12 years ago
- 35e1c86 VIA southbridge K8T890: Apply un-written naming rules by Kyösti Mälkki · 12 years ago
- 5750ed2 Fix AMD Fam14 cbmen allocation by Marc Jones · 12 years ago
- 8d59569 Clean up whitespace in fam14 northbridge.c by Marc Jones · 12 years ago
- c5fc7db Move C labels to start-of-line by Patrick Georgi · 12 years ago
- 067d223 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. by Marc Jones · 12 years ago
- 334328a Avoid ../../.. paths in ASL files by Patrick Georgi · 13 years ago
- fdcd135 Rename i945 ACPI files to not carry an i945_ prefix by Patrick Georgi · 13 years ago
- 472efa6 Remove whitespace. by Patrick Georgi · 13 years ago
- 6811f75 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper by Kerry Sheh · 13 years ago
- 6b909f2 RD890: AMD RD890/SR56X0 CIMX wrapper by Kerry Sheh · 13 years ago
- bdc8c83 Remove non-existent include by Sven Schnelle · 13 years ago
- 332a7e9 i5000: halt second BSP by Sven Schnelle · 13 years ago
- 1767086 Add Intel i5000 Memory Controller Hub by Sven Schnelle · 13 years ago
- 751508a northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option by Peter Stuge · 13 years ago
- 976f8cc Make Geode GX2 VGA setup work. by Nils Jacobs · 13 years ago
- 784ffb3 i945: fix tsc udelay() by Sven Schnelle · 13 years ago
- d0ac789 Update geode GX2 tree to match LX. by Nils Jacobs · 13 years ago
- 84e0dfc Clean up AMD Fam14 SSDT by Marc Jones · 13 years ago
- a4f06f1 White space and coding style fixes. by Nils Jacobs · 13 years ago
- 36b53bf k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x by Florian Zumbiehl · 13 years ago
- 2a830d0 Change AMD vendorcode build by Kyösti Mälkki · 13 years ago
- fa48b96 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 by Florian Zumbiehl · 13 years ago
- 6f7b158 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit by Florian Zumbiehl · 13 years ago
- 7e9de01 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 by Florian Zumbiehl · 13 years ago
- 5ff7c13 remove trailing whitespace by Stefan Reinauer · 13 years ago
- 0a0d5e8 Add support for E7505 northbridge. by Kyösti Mälkki · 13 years ago
- 481814d Clear improper use of CONFIG_CACHE_AS_RAM by Kyösti Mälkki · 13 years ago
- b15975b copy e7501 component to e7505 by Stefan Reinauer · 13 years ago
- 5563959 I945: replace #if defined() by #if by Sven Schnelle · 13 years ago
- 328a694 AMD CPU and chipset fixes for compilation with gcc 4.6 by Stefan Reinauer · 13 years ago
- ab87254 use acpi.h include instead of manually adding acpi_slp_type. by Stefan Reinauer · 13 years ago
- 86fc984 Fix compilation of AMD GX2 northbridge code with gcc 4.6 by Stefan Reinauer · 13 years ago
- 89fcdec Fix compilation of VIA CN700 northbridge code with gcc 4.6 by Stefan Reinauer · 13 years ago
- b9d60c9 fix compilation of intel/sch northbridge code with gcc 4.6 by Stefan Reinauer · 13 years ago
- 80311ea amdk8: ASL include for K8 temperature sensor support in ACPI by Christoph Grenz · 13 years ago
- af90275 TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platforms by enok71 · 13 years ago
- 8eb4273 Add AMD Family 10h PH-E0 support by QingPei Wang · 13 years ago
- 3f5ebd6 AMD F14 Northbridge updates by efdesign98 · 13 years ago
- 03169d3 Replace while with do; while to avoid repetition by Noe Rubinstein · 13 years ago
- 7981b94 Report GSE chipset and warn if the code has been compiled for the wrong chipset. by Stefan Reinauer · 13 years ago
- feed329 AMD F14 southbridge update by Kerry She · 13 years ago
- e089a3f northbridge/intel/i440bx: Registered SDRAM modules support and fixes by Keith Hui · 13 years ago
- 00c8c4a Update AMD SR5650 and SB700 by efdesign98 · 13 years ago
- b58640c Add AMD Family 10 cpu support to northbridge folder by efdesign98 · 13 years ago
- 7d6f0bf ASRock E350M1: ACPI-related BSOD fix by Scott Duplichan · 13 years ago
- 1fe6c64 Fix memory size reporting on AMD family 14h systems for >= 4GB by Cristian Măgherușan-Stanciu · 13 years ago
- 23b2152 Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP and by Rudolf Marek · 13 years ago
- 7c0c64e Addition of Family12/SB900 wrapper code by efdesign98 · 13 years ago
- 621ca38 Move existing AMD Ffamily14 code to f14 folder by efdesign98 · 13 years ago
- 05a89ab Rename {CPU|NB|SB}/amd/*_wrapper folders by efdesign98 · 13 years ago
- b629d14 i945 GMA: restore tft brightness from cmos by Sven Schnelle · 13 years ago
- d8c68a9 i82801gx: replace cafed00d/cafebabe by defines by Sven Schnelle · 13 years ago
- 471f103 This patch sets max freq defaults for ddr2 and ddr3for fam10. by Marc Jones · 13 years ago
- 16c8e37 agesa_wrapper: Avoid repetitive Kconfig depends, trivial by Peter Stuge · 13 years ago
- 8c46263 Cosmetic cleanup. by Scott Duplichan · 13 years ago
- 5d878ad 1) Remove unused kconfig options. 2) Correct UMA graphics PCI device ID. by Scott Duplichan · 13 years ago
- 9ab3c6c Build device paths for AP cores so that coreboot will report them to the OS. by Scott Duplichan · 13 years ago
- dc312cc Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR. by Scott Duplichan · 13 years ago
- 8d6cf3a Work around unclean CMOS handling for now by Patrick Georgi · 13 years ago
- b251753 Change read_option() to a macro that wraps some API uglyness by Patrick Georgi · 13 years ago
- d4814bd more ifdef -> if fixes by Stefan Reinauer · 13 years ago
- 1d888a9 some ifdef --> if fixes by Stefan Reinauer · 13 years ago
- b18f9b0 The "temp" will be used later. So it has to be calculated correctly. by Zheng Bao · 13 years ago
- 432461e cleanup wrong use of defined() after exporting all variables in Kconfig by Stefan Reinauer · 13 years ago
- 8902502 drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCH by Stefan Reinauer · 13 years ago
- 5005bb06 Unify use of post_code by Alexandru Gagniuc · 13 years ago
- 148a4f5 i945: improve get_top_of_ram() by Sven Schnelle · 13 years ago
- 2ca2f17 Add AMD C32 support. It is based on other existing Fam10 code. by Zheng Bao · 13 years ago
- 314dd0b Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF. by Scott Duplichan · 13 years ago
- 11ac1cf Mark non-returning function as noreturn to help some compiler versions by Patrick Georgi · 13 years ago
- 6bdc83b Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
- c313210 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago