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review.coreboot.org / coreboot / 806fa2463f16d32f98cff6437576a5efe2874ece / src / soc / intel / broadwell / spi.c
  1. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  2. 4460703 Drop "See file CREDITS..." comment by Stefan Reinauer · 9 years ago
  3. 4d3de7e bootstate: remove need for #ifdef ENV_RAMSTAGE by Aaron Durbin · 9 years ago
  4. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  5. 40e2004 intel/broadwell: bootstate mechanism only exists in ramstage by Patrick Georgi · 9 years ago
  6. f059b24 broadwell: Add function to apply PRR to a range of SPI flash by Duncan Laurie · 10 years ago
  7. 4ee4bd5 broadwell: Change all SoC headers to <soc/headername.h> system by Julius Werner · 10 years ago
  8. 9ef9d85 bootstate: use structure pointers for scheduling callbacks by Aaron Durbin · 9 years ago
  9. bde6d30 x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer by Kevin Paul Herbert · 10 years ago
  10. a6354a1 broadwell: Preparations for building by Marc Jones · 10 years ago
  11. de7ed6f intel/broadwell: Spelling fixes by Martin Roth · 10 years ago
  12. c88c54c broadwell: add new intel SOC by Duncan Laurie · 10 years ago