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review.coreboot.org / coreboot / 7b523a4be90f6e825d1947bdddc86180f72914c7 / src / soc / intel / alderlake / fsp_params.c
  1. 7b523a4 soc/intel/alderlake: Use intel_microcode_find() to locate ucode.bin by Subrata Banik · 2 years, 11 months ago
  2. eafca1f soc/intel/alderlake: Switch to using device pointers by Furquan Shaikh · 2 years, 11 months ago
  3. 298b359 drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling method by Subrata Banik · 3 years ago
  4. e2b8f30 soc/intel/alderlake: Set LpmStateEnableMask UPD by Tim Wawrzynczak · 3 years, 1 month ago
  5. 091dfa1 soc/intel/alderlake: Lock PAM registers in finalize by Tim Wawrzynczak · 3 years ago
  6. f9d7dc7 soc/intel/alderlake: Clean up FSP chipset lockdown configuration by Felix Singer · 3 years, 4 months ago
  7. c6d7166 soc/intel/alderlake: Configure the SKU specific parameters for VR domains by V Sowmya · 3 years, 1 month ago
  8. 458708f soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL by V Sowmya · 3 years, 1 month ago
  9. bc35bed soc/intel/*: Allow configuring 8254 timer via CMOS by Sean Rhodes · 3 years, 1 month ago
  10. 87685c5 soc/intel/alderlake: Make use of `cpu/intel/cpu_ids.h' by Subrata Banik · 3 years, 1 month ago
  11. 82225b8 soc/intel/alderlake: Add (and fix) devices in IRQ table by Tim Wawrzynczak · 3 years, 1 month ago
  12. af42906 soc/intel/alderlake: Set max Pkg C-states to Auto by V Sowmya · 3 years, 2 months ago
  13. 418d37e soc/intel/alderlake: Add support to update the FIVR configs by V Sowmya · 3 years, 2 months ago
  14. 421ce56 soc/intel/alderlake: Add USB TCSS enablement by Bernardo Perez Priego · 3 years, 2 months ago
  15. 844dcb3 soc/intel/alderlake: Enable energy efficiency turbo mode by V Sowmya · 3 years, 2 months ago
  16. c7cfe0b soc/intel: Refactor `xdci_can_enable()` function by Angel Pons · 3 years, 2 months ago
  17. c0e82e7 soc/intel/alderlake: Send End-of-Post message to CSE by Tim Wawrzynczak · 3 years, 2 months ago
  18. 43607e4 soc/intel/alderlake: Enable support for common IRQ block by Tim Wawrzynczak · 3 years, 3 months ago
  19. 6464c2a soc/intel/alderlake: Fix the typo for FSP_S_CONFIG param by V Sowmya · 3 years, 2 months ago
  20. b03cadf soc/intel/alderlake: Refactor soc_silicon_init_params function by Subrata Banik · 3 years, 2 months ago
  21. c0983c9 soc/intel/alderlake: Rename FSP_S_CONFIG variable from params to s_cfg by Subrata Banik · 3 years, 2 months ago
  22. 6f1cb40 soc/intel/alderlake: Refactor platform_fsp_silicon_init_params_cb function by Subrata Banik · 3 years, 2 months ago
  23. e633804 soc/intel/alderlake: Use devfn_disable() function for XDCI by Subrata Banik · 3 years, 2 months ago
  24. 095f97b soc/intel/alderlake: Add TBT PCIe root ports enablement by Bernardo Perez Priego · 3 years, 3 months ago
  25. 50134ec soc/intel/alderlake: Make use of is_devfn_enabled() function by Subrata Banik · 3 years, 2 months ago
  26. b9b6f4d soc/intel: Drop unused lpss functions by Furquan Shaikh · 3 years, 3 months ago
  27. 8e7facf soc/intel/alderlake: mb/intel/sm: Add tcss code by Deepti Deshatty · 3 years, 3 months ago
  28. 6935350 soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC by Maulik V Vaghela · 3 years, 4 months ago
  29. bc1941f soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entry by Cliff Huang · 3 years, 6 months ago
  30. 812b54e soc/intel/alderlake: Set LidStatus UPD if RUN_FSP_GOP selected by Ronak Kanabar · 3 years, 6 months ago
  31. 5b302b2 soc/intel/alderlake: Refactor PCIE port config by Eric Lai · 3 years, 9 months ago
  32. 85144d9 soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs by Subrata Banik · 3 years, 7 months ago
  33. 99289a8 soc/intel/alderlake: Update CPU microcode patch base address/size by Subrata Banik · 3 years, 8 months ago
  34. 2871e0e soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage by Subrata Banik · 3 years, 11 months ago