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review.coreboot.org / coreboot / 751508ab019e0612f715ea481c550d73aa240112 / src / northbridge
  1. 751508a northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option by Peter Stuge · 13 years ago
  2. 976f8cc Make Geode GX2 VGA setup work. by Nils Jacobs · 13 years ago
  3. 784ffb3 i945: fix tsc udelay() by Sven Schnelle · 13 years ago
  4. d0ac789 Update geode GX2 tree to match LX. by Nils Jacobs · 13 years ago
  5. 84e0dfc Clean up AMD Fam14 SSDT by Marc Jones · 13 years ago
  6. a4f06f1 White space and coding style fixes. by Nils Jacobs · 13 years ago
  7. 36b53bf k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x by Florian Zumbiehl · 13 years ago
  8. 2a830d0 Change AMD vendorcode build by Kyösti Mälkki · 13 years ago
  9. fa48b96 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 by Florian Zumbiehl · 13 years ago
  10. 6f7b158 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit by Florian Zumbiehl · 13 years ago
  11. 7e9de01 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 by Florian Zumbiehl · 13 years ago
  12. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 13 years ago
  13. 0a0d5e8 Add support for E7505 northbridge. by Kyösti Mälkki · 13 years ago
  14. 481814d Clear improper use of CONFIG_CACHE_AS_RAM by Kyösti Mälkki · 13 years ago
  15. b15975b copy e7501 component to e7505 by Stefan Reinauer · 13 years ago
  16. 5563959 I945: replace #if defined() by #if by Sven Schnelle · 13 years ago
  17. 328a694 AMD CPU and chipset fixes for compilation with gcc 4.6 by Stefan Reinauer · 13 years ago
  18. ab87254 use acpi.h include instead of manually adding acpi_slp_type. by Stefan Reinauer · 13 years ago
  19. 86fc984 Fix compilation of AMD GX2 northbridge code with gcc 4.6 by Stefan Reinauer · 13 years ago
  20. 89fcdec Fix compilation of VIA CN700 northbridge code with gcc 4.6 by Stefan Reinauer · 13 years ago
  21. b9d60c9 fix compilation of intel/sch northbridge code with gcc 4.6 by Stefan Reinauer · 13 years ago
  22. 80311ea amdk8: ASL include for K8 temperature sensor support in ACPI by Christoph Grenz · 13 years ago
  23. af90275 TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platforms by enok71 · 13 years ago
  24. 8eb4273 Add AMD Family 10h PH-E0 support by QingPei Wang · 13 years ago
  25. 3f5ebd6 AMD F14 Northbridge updates by efdesign98 · 13 years ago
  26. 03169d3 Replace while with do; while to avoid repetition by Noe Rubinstein · 13 years ago
  27. 7981b94 Report GSE chipset and warn if the code has been compiled for the wrong chipset. by Stefan Reinauer · 13 years ago
  28. feed329 AMD F14 southbridge update by Kerry She · 13 years ago
  29. e089a3f northbridge/intel/i440bx: Registered SDRAM modules support and fixes by Keith Hui · 13 years ago
  30. 00c8c4a Update AMD SR5650 and SB700 by efdesign98 · 13 years ago
  31. b58640c Add AMD Family 10 cpu support to northbridge folder by efdesign98 · 13 years ago
  32. 7d6f0bf ASRock E350M1: ACPI-related BSOD fix by Scott Duplichan · 13 years ago
  33. 1fe6c64 Fix memory size reporting on AMD family 14h systems for >= 4GB by Cristian Măgherușan-Stanciu · 13 years ago
  34. 23b2152 Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP and by Rudolf Marek · 13 years ago
  35. 7c0c64e Addition of Family12/SB900 wrapper code by efdesign98 · 13 years ago
  36. 621ca38 Move existing AMD Ffamily14 code to f14 folder by efdesign98 · 13 years ago
  37. 05a89ab Rename {CPU|NB|SB}/amd/*_wrapper folders by efdesign98 · 13 years ago
  38. b629d14 i945 GMA: restore tft brightness from cmos by Sven Schnelle · 13 years ago
  39. d8c68a9 i82801gx: replace cafed00d/cafebabe by defines by Sven Schnelle · 13 years ago
  40. 471f103 This patch sets max freq defaults for ddr2 and ddr3for fam10. by Marc Jones · 13 years ago
  41. 16c8e37 agesa_wrapper: Avoid repetitive Kconfig depends, trivial by Peter Stuge · 13 years ago
  42. 8c46263 Cosmetic cleanup. by Scott Duplichan · 13 years ago
  43. 5d878ad 1) Remove unused kconfig options. 2) Correct UMA graphics PCI device ID. by Scott Duplichan · 13 years ago
  44. 9ab3c6c Build device paths for AP cores so that coreboot will report them to the OS. by Scott Duplichan · 13 years ago
  45. dc312cc Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR. by Scott Duplichan · 13 years ago
  46. 8d6cf3a Work around unclean CMOS handling for now by Patrick Georgi · 13 years ago
  47. b251753 Change read_option() to a macro that wraps some API uglyness by Patrick Georgi · 13 years ago
  48. d4814bd more ifdef -> if fixes by Stefan Reinauer · 13 years ago
  49. 1d888a9 some ifdef --> if fixes by Stefan Reinauer · 13 years ago
  50. b18f9b0 The "temp" will be used later. So it has to be calculated correctly. by Zheng Bao · 13 years ago
  51. 432461e cleanup wrong use of defined() after exporting all variables in Kconfig by Stefan Reinauer · 13 years ago
  52. 8902502 drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCH by Stefan Reinauer · 13 years ago
  53. 5005bb06 Unify use of post_code by Alexandru Gagniuc · 13 years ago
  54. 148a4f5 i945: improve get_top_of_ram() by Sven Schnelle · 13 years ago
  55. 2ca2f17 Add AMD C32 support. It is based on other existing Fam10 code. by Zheng Bao · 13 years ago
  56. 314dd0b Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF. by Scott Duplichan · 13 years ago
  57. 11ac1cf Mark non-returning function as noreturn to help some compiler versions by Patrick Georgi · 13 years ago
  58. 6bdc83b Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  59. c313210 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  60. 6276b6f Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  61. 82b241a Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  62. 5bcedee Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  63. ce62350 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  64. e80ce0a Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  65. 26f97d2 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  66. 19245c9 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  67. e485aa4 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  68. 1f93fea Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  69. 0e5d3e1 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  70. adb23a5 Improving BKDG implementation of P-states, by Xavi Drudis Ferran · 13 years ago
  71. 70a3733 Add 300 MHz and 500 MHz HT frequency limits by Xavi Drudis Ferran · 13 years ago
  72. ed1d116 Add compile-time defaults to some K8 CMOS options in case they're absent in CMOS by Josef Kellermann · 13 years ago
  73. 541269b [i945] Add SPD adress mapping by Sven Schnelle · 13 years ago
  74. f0ccf6e Errata #169 works on HT, not MC by Josef Kellermann · 14 years ago
  75. 39fca80 This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code. by Frank Vibrans · 14 years ago
  76. 1df8542 Implemented workaround for erratum 169, obsoleting erratum 131. by Alexandru Gagniuc · 14 years ago
  77. 4096fc5 SMM code on i945 platforms needs udelay() by Peter Stuge · 14 years ago
  78. dd676dd For Cx, each ChipSel need to be sent MR command. by Zheng Bao · 14 years ago
  79. c29675f Add a GX2 Kconfig option to choose the framebuffer size. by Nils Jacobs · 14 years ago
  80. a7296e7 The code is tested on my board with register DIMMs. More tests need to be by Zheng Bao · 14 years ago
  81. 69436e1 Fix some settings fo AMD MCT. It is based on BIOS test suite. by Zheng Bao · 14 years ago
  82. 8cf54c9 Use die() to assure the processor can't wake up from an interrupt. by Nils Jacobs · 14 years ago
  83. 84be0f5 -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port) by Nils Jacobs · 14 years ago
  84. cdcf983 fix i810 boards with ram init debugging disabled. by Stefan Reinauer · 14 years ago
  85. fc01e5e proper printk handling in src/northbridge/intel/i82810/raminit.c by Stefan Reinauer · 14 years ago
  86. 50e7233 __PRE_RAM__ is defined by the makefile by Stefan Reinauer · 14 years ago
  87. 1c2c750 dump_spd_registers() is only defined when ram init debugging is on. by Stefan Reinauer · 14 years ago
  88. 3c0bfaf Fix most CONFIG_DEBUG_RAM_SETUP issues. by Stefan Reinauer · 14 years ago
  89. 19d69e3 Move Geode GX2 UMA video memory size to Kconfig by Nils Jacobs · 14 years ago
  90. 642509c Remove dead and unused Geode GX2 code by Nils Jacobs · 14 years ago
  91. 3344743 Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names by Nils Jacobs · 14 years ago
  92. 1c6d4e6 Clean up Geode GX2 comments, whitespace and coding style. Trivial. by Nils Jacobs · 14 years ago
  93. 09f5a74 Fix build with CONFIG_DEBUG_RAM_SETUP on Intel 440BX, use printk(). by Keith Hui · 14 years ago
  94. bccbbe6 The same mechanisms are used for normal and fallback images. by Stefan Reinauer · 14 years ago
  95. 405721d Fix a few whitespace and coding style issues. by Uwe Hermann · 14 years ago
  96. a0360af A couple of Poulsbo fixes: by Patrick Georgi · 14 years ago
  97. be61a17 Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board which uses it. by Patrick Georgi · 14 years ago
  98. 85b0fa1 drop one more version of doing serial uart output differently. by Stefan Reinauer · 14 years ago
  99. 259a39f fix according to coding guidelines by Stefan Reinauer · 14 years ago
  100. cc1e645 Attached patch implements the memory speed reductions (and 2T/1T clock logic) for DDR1 memory (939 sockets). The details can be found in BKDG chapter 4.1.3.3. by Rudolf Marek · 14 years ago