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review.coreboot.org / coreboot / 6f72d6965c7c54df663f2337e6154daf4dd464ff / src / include
  1. 6f72d69 Add timestamp collecting to coreboot. by Vadim Bendebury · 13 years ago
  2. e186060 Initialize CBMEM early. by Vadim Bendebury · 13 years ago
  3. 1c89e90 Add RDC R8610 PCI IDs. by Rudolf Marek · 12 years ago
  4. 1a34165 xchg is atomic with side-effects by Patrick Georgi · 13 years ago
  5. 02bb578 Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available by Gabe Black · 13 years ago
  6. 294edb2 Increase size of the coreboot table area by Stefan Reinauer · 13 years ago
  7. 6f88a6e Add helper function to find a Local APIC by ID in the device tree. by Duncan Laurie · 13 years ago
  8. 8907e81 move console includes to central console/console.h by Stefan Reinauer · 13 years ago
  9. 1025f3a Add an implementation for the memchr library function by Gabe Black · 13 years ago
  10. c8feedd Unify Local APIC address definitions by Patrick Georgi · 13 years ago
  11. e41745e pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids by Kerry Sheh · 13 years ago
  12. d3e990c AGESA F15: AGESA family15 model 00-0fh cpu wrapper by Kerry Sheh · 13 years ago
  13. 7916f4c AMD Geode cpus: apply un-written naming rules by Kyösti Mälkki · 13 years ago
  14. c0a6c6b Add OPROM mapping support to coreboot by Stefan Reinauer · 13 years ago
  15. 52bfa4d RD890: pci_ids update by Kerry Sheh · 13 years ago
  16. 0713ca3 post code: Replaced hard-coded post code with macro by Vikram Narayanan · 13 years ago
  17. 3ad8c54 lib: add ram_check_nodie by Sven Schnelle · 13 years ago
  18. adfbcb79 MTRR: get physical address size from CPUID by Sven Schnelle · 13 years ago
  19. a27561c Fix CMOS handling for non-USE_OPTION_TABLE configuration by Patrick Georgi · 13 years ago
  20. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 13 years ago
  21. 784544b Remove XIP_ROM_BASE by Patrick Georgi · 13 years ago
  22. 20fc631 Fix usb debug dongle support by Sven Schnelle · 13 years ago
  23. 1da1046 Get rid of AUTO_XIP_ROM_BASE by Patrick Georgi · 13 years ago
  24. d1bc331 Extend coreboot table entry for serial ports by Stefan Reinauer · 13 years ago
  25. 9ea33e9 Add macros for 64bit byte order swapping by Stefan Reinauer · 13 years ago
  26. 491e2a2 Enable/fix compilation of i8254 code in ram stage. by Stefan Reinauer · 13 years ago
  27. 0e6344e SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode by Kerry Sheh · 13 years ago
  28. f8adf7a pci_ids: Add sb800 SATA device raid mode device id by Kerry Sheh · 13 years ago
  29. 83d59b9 Build warning fix for AMD Family 12 by efdesign98 · 13 years ago
  30. 78834b7 Miscellaneous AMD F14 warning fixes by efdesign98 · 13 years ago
  31. 7f0e930 Add support for the tracing infastructure in coreboot. by Rudolf Marek · 13 years ago
  32. 164bcfd Add automatic SMBIOS table generation by Sven Schnelle · 13 years ago
  33. d819853 export get_cbfs_header() by Sven Schnelle · 13 years ago
  34. b883515 split CBFS support into shared core and extended functions by Patrick Georgi · 13 years ago
  35. 1ac19e2 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. by Keith Hui · 13 years ago
  36. b5b3b3b Make AMD SMM SMP aware by Rudolf Marek · 13 years ago
  37. a68555f Do full flush on uart8250 only at end of printk. by Kevin O'Connor · 13 years ago
  38. 7c0c64e Addition of Family12/SB900 wrapper code by efdesign98 · 13 years ago
  39. 180f81e SMM: add guard and include types.h in cpu/x86/smm.h by Sven Schnelle · 13 years ago
  40. bfe8e51 SMM: don't overwrite SMM memory on resume by Sven Schnelle · 13 years ago
  41. d29e5bb CMOS: add set_option() by Sven Schnelle · 13 years ago
  42. f4dc1a7 SMM: add defines for APM_CNT register by Sven Schnelle · 13 years ago
  43. c21b054 SMM: add mainboard_apm_cnt() callback by Sven Schnelle · 13 years ago
  44. 23d3dfa Correct wrong PCI ID for VIA K8M890 Chrome. by Alexandru Gagniuc · 13 years ago
  45. 8c46263 Cosmetic cleanup. by Scott Duplichan · 13 years ago
  46. f191c72 Enable AHCI mode and hide IDE controller to reduce boot time. by Scott Duplichan · 13 years ago
  47. b251753 Change read_option() to a macro that wraps some API uglyness by Patrick Georgi · 13 years ago
  48. f2ed23f Adds RS740 HT and internal graphics PCI ids. by Ivaylo Valkov · 13 years ago
  49. 4885daa Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an by Stefan Reinauer · 13 years ago
  50. 6aca1e8 The UART divider should be calculated based on the base frequency by Stefan Reinauer · 13 years ago
  51. d4814bd more ifdef -> if fixes by Stefan Reinauer · 13 years ago
  52. 1d888a9 some ifdef --> if fixes by Stefan Reinauer · 13 years ago
  53. bbd2f21 Simplify coreboot's console/console.h by Stefan Reinauer · 13 years ago
  54. 20f7f3b pci1x2x: add PCI1510 device IDs by Sven Schnelle · 13 years ago
  55. b297b49 drop dead uart init code. by Stefan Reinauer · 13 years ago
  56. 5005bb06 Unify use of post_code by Alexandru Gagniuc · 13 years ago
  57. 61aee5f In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__. by Stefan Reinauer · 13 years ago
  58. 98fcc09 Add AMD SR56x0 support. by Zheng Bao · 13 years ago
  59. b8269e2 Fix a simple whitespace error in src/include/device/device.h by Sven Schnelle · 14 years ago
  60. 270a908 Add subsystemid option to sconfig by Sven Schnelle · 14 years ago
  61. 025ead7 Extended K8T890 driver to include the K8T800 and K8M800 northbridges by Alexandru Gagniuc · 14 years ago
  62. 6b4674e I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347. by Frank Vibrans · 14 years ago
  63. 87fcffa Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functions by Patrick Georgi · 14 years ago
  64. 38b1f3b Add PCI ID's for VIA K8T800 and K8M800 northbridges. by Alexandru Gagniuc · 14 years ago
  65. 16ce01b This patch gets usbdebug console working in romstage. by Stefan Reinauer · 14 years ago
  66. 7b0500c Revert r5902 to make code more readable again. At least three people like to by Stefan Reinauer · 14 years ago
  67. 5bb9fd6 Now that the VIA code is run above 1Meg (like other boards), it should by Kevin O'Connor · 14 years ago
  68. 2447937 Move option table (cmos.layout's binary representation) by Patrick Georgi · 14 years ago
  69. 84f59ae Add AMD SB800 southbridge support via cimx_wrapper. by Kerry She · 14 years ago
  70. 40992d3 Add RS785(RS880) support. Just few pci_ids. by Zheng Bao · 14 years ago
  71. 84be0f5 -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port) by Nils Jacobs · 14 years ago
  72. 3344743 Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names by Nils Jacobs · 14 years ago
  73. 1c6d4e6 Clean up Geode GX2 comments, whitespace and coding style. Trivial. by Nils Jacobs · 14 years ago
  74. cadc545 SMM for AMD K8 Part 1/2 by Stefan Reinauer · 14 years ago
  75. 3817494 fix the tree again. by Stefan Reinauer · 14 years ago
  76. 85b0fa1 drop one more version of doing serial uart output differently. by Stefan Reinauer · 14 years ago
  77. efbfd50 guard against the case that CONFIG_WAIT_BEFORE_CPUS_INIT is not defined at all. by Stefan Reinauer · 14 years ago
  78. 475916d Compile cbmem.c instead of including it in romstage, by Rudolf Marek · 14 years ago
  79. 97be27e We hardcode highmemory size in every northbridge! This is bad, and especially if suspend to ram is involved. Let the default be taken from cbmem.h which also handles the suspend logic. by Rudolf Marek · 14 years ago
  80. 3310934 Following patch makes just one fadt.c file. For SB700. by Rudolf Marek · 14 years ago
  81. 2a27b20 factor out cpu power management base into a separate file. And fix a bug in by Stefan Reinauer · 14 years ago
  82. 8677a23 After this has been brought up many times before, rename src/arch/i386 to by Stefan Reinauer · 14 years ago
  83. 8301d83 second round name simplification. drop the <component>_ prefix. by stepan · 14 years ago
  84. 3a4ed15 W83627DHG/W83627EHG fixups for virtual LDNs. by Uwe Hermann · 14 years ago
  85. bcaea14 1) wraps the s3 parts of chipset code/memory init code with if CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c by Rudolf Marek · 14 years ago
  86. abc0c85 Printing coreboot debug messages on VGA console is pretty much useless, since by Stefan Reinauer · 14 years ago
  87. d773fd3 Some more DIMM0 related cleanups and deduplication. by Uwe Hermann · 14 years ago
  88. 9bd9a90 Unify DIMM SPD addressing. For Geode, change the by Patrick Georgi · 14 years ago
  89. d491769 For completeness sake: License header. by Patrick Georgi · 14 years ago
  90. 361bd10 Move Intel power management related defines to some central location. by Patrick Georgi · 14 years ago
  91. f3cce2f MTRR related improvements for AMD family 10h and family 0Fh systems by Scott Duplichan · 14 years ago
  92. e080bca Add pci id and ops for VT8237A SATA controller by Tobias Diedrich · 14 years ago
  93. 2210135 This adds the VT8237A LPC device id and the pci_driver struct in vt8237r_lpc.c by Tobias Diedrich · 14 years ago
  94. e487047 Various cosmetic and coding style fixes in src/devices. by Uwe Hermann · 14 years ago
  95. d50b43a This adds pci device ids and pci_driver structs for the K8T890 CF by Tobias Diedrich · 14 years ago
  96. 76890dd Change Geode GX2 to use the auto DRAM detect code from Geode LX. by Nils Jacobs · 14 years ago
  97. 809e29e GX2: Clean up some white space and comments. by Nils Jacobs · 14 years ago
  98. d453dd0 Cosmetics and coding style fixes in devices/*. by Uwe Hermann · 14 years ago
  99. 4ffde94 Reduce duplicate definition in CAR code. by Warren Turkal · 14 years ago
  100. 4b42a62 Factor out a few commonly duplicated functions from northbridge.c. by Uwe Hermann · 14 years ago