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review.coreboot.org / coreboot / 6e98292821ad70ebf970d2ae90faa062d960a5bf / src / soc / intel / tigerlake / chip.h
  1. 6e98292 soc/intel/*/chip: Remove unused devicetree entry by Patrick Rudolph · 3 years, 10 months ago
  2. a64b4f4 mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` by Michael Niewöhner · 3 years, 10 months ago
  3. 0d0f43f soc/intel/tigerlake: Add Acoustic features by Shaunak Saha · 4 years ago
  4. 5b7daa2 soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widths by Jamie Ryu · 4 years ago
  5. 9fec889 soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.h by Subrata Banik · 4 years ago
  6. 6fd87ff soc/intel/tigerlake: Allow fine grained control of S0iX states by Jes Klinke · 4 years ago
  7. bd615d6 soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold by John Zhao · 4 years, 1 month ago
  8. 23a60fa src/soc/intel: Add include <types.h> by Elyes HAOUAS · 4 years, 1 month ago
  9. 1a62150 soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU by Sumeet R Pawnikar · 4 years, 1 month ago
  10. 1a8949c soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDs by Shaunak Saha · 4 years, 2 months ago
  11. 8104eff mainboard/intel/tglrvp: Remove unused PrmrrSize chip config by Subrata Banik · 4 years, 1 month ago
  12. f8668e9 soc/intel/tigerlake: Add CpuReplacementCheck to chip options by Jamie Ryu · 4 years, 2 months ago
  13. 63ce260 soc/intel/tigerlake: Add CmdMirror option in chip.h by David Wu · 4 years, 2 months ago
  14. 2dcca0f mb/google/volteer: Override power limits with SKU-specific limits by Tim Wawrzynczak · 4 years, 2 months ago
  15. c66c153 soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD by Wonkyu Kim · 4 years, 3 months ago
  16. e18f719 soc/intel/tigerlake: Add devicetree support to change PCH VR settings by Venkata Krishna Nimmagadda · 4 years, 3 months ago
  17. 92a3a30 soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs by John Zhao · 4 years, 3 months ago
  18. 23e8b5b soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En by John Zhao · 4 years, 3 months ago
  19. b30fe36 soc/intel/tigerlake: Remove MIPI clock setting from devicetree by Srinidhi N Kaushik · 4 years, 3 months ago
  20. b4d7116 soc/intel/tigerlake: Delete unused configuration by Wonkyu Kim · 4 years, 3 months ago
  21. 8aac881 soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnable by John Zhao · 4 years, 3 months ago
  22. d213246 tigerlake: update processor power limits configuration by Sumeet R Pawnikar · 4 years, 3 months ago
  23. 71d365d soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfg by Brandon Breitenstein · 4 years, 4 months ago
  24. 7a05e6e soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En by John Zhao · 4 years, 3 months ago
  25. 54b706e soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect override by Eric Lai · 4 years, 3 months ago
  26. 32b8a51 soc/intel/tigerlake: Control SATA and DMI power optimization by Shaunak Saha · 4 years, 5 months ago
  27. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
  28. 7be0df8 soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understanding by Subrata Banik · 4 years, 4 months ago
  29. 0d6cc22 soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree by Meera Ravindranath · 4 years, 4 months ago
  30. 04a8cfb soc/intel/tigerlake: Update iDisp Link UPD settings by Srinidhi N Kaushik · 4 years, 4 months ago
  31. 3ed55e5 soc/intel/tigerlake: Remove eMMC/SD support by Duncan Laurie · 4 years, 4 months ago
  32. 5943117 soc/intel/tigerlake: Configure RP setting by Wonkyu Kim · 4 years, 4 months ago
  33. 16f6aa8 soc/intel/tigerlake: Use SPDX for GPL-2.0-only files by Angel Pons · 4 years, 5 months ago
  34. fc93237 soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3 by Brandon Breitenstein · 4 years, 5 months ago
  35. 3180af7 soc/intel/tigerlake: Configure Hyperthreading by Wonkyu Kim · 4 years, 5 months ago
  36. 1c6d8a9 soc: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
  37. a6bff2d soc/intel/tigerlake: Enable CNVi through dev_enabled by Srinidhi N Kaushik · 4 years, 5 months ago
  38. 4b9fa2d soc/intel/tigerlake: Update Cpu Ratio settings by Srinidhi N Kaushik · 4 years, 5 months ago
  39. 84b4882 soc/intel/tigerlake: Configure L1Substates for PCH Root ports by Wonkyu Kim · 4 years, 5 months ago
  40. 35d7843 soc/intel/tigerlake: Correct FSP log interface by Ronak Kanabar · 4 years, 6 months ago
  41. 2b4ded0 soc/intel/tigerlake: Enable Hybrid storage mode by Wonkyu Kim · 4 years, 6 months ago
  42. 8488853 soc/intel/tigerlake: Enable CNVi Mode by Srinidhi N Kaushik · 4 years, 6 months ago
  43. 79ccc69 src: capitalize 'PCIe' by Elyes HAOUAS · 4 years, 6 months ago
  44. 1c2313d soc/intel/tigerlake: Add Jasper lake GPIO support by Ronak Kanabar · 4 years, 8 months ago
  45. 56626cf soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig by Subrata Banik · 4 years, 6 months ago
  46. dba6c4c soc/intel/tigerlake: Update FSP params for Jasper Lake by Maulik V Vaghela · 4 years, 7 months ago
  47. 2f2c7eb soc/intel/tigerlake: Enable Audio on TGL by Srinidhi N Kaushik · 4 years, 8 months ago
  48. 1ab6f0c soc/intel/tigerlake: Configure TCSS xHCI and xDCI by Wonkyu Kim · 4 years, 7 months ago
  49. 9f2e3ad soc/intel/tigerlake: Enable DP ports according to board design by Wonkyu Kim · 4 years, 7 months ago
  50. 2fd4972 soc/intel/tigerlake: Update chip files by Ravi Sarawadi · 4 years, 8 months ago
  51. a6eab80 soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h by Furquan Shaikh · 4 years, 8 months ago
  52. 91e89c5 soc/intel/tigerlake: Do initial SoC commit till ramstage by Subrata Banik · 4 years, 10 months ago