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review.coreboot.org / coreboot / 66b0d55d326540e400ad3fa5130666dbd03b9694 / src / soc / intel / baytrail / chip.h
  1. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  2. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  3. ba9b7bf baytrail: add code for supporting 2x ddr refresh rate by Kane Chen · 10 years ago
  4. 314c4c3 baytrail: use the setting in devicetree.cb to config USBPHY_COMPBG by Kane Chen · 10 years ago
  5. 59e209a baytrail: initialize backlight PWM frequency by Aaron Durbin · 10 years ago
  6. dd20d5d baytrail: Remove unused devicetree fields by Shawn Nematbakhsh · 10 years ago
  7. 3511023 baytrail/rambi: S3 support and other updates by Kein Yuan · 11 years ago
  8. 51d787a rambi/baytrail: ACPI, GPIO, audio, misc updates by Shawn Nematbakhsh · 11 years ago
  9. 430bf0d baytrail: Add support for LPSS and SCC devices in ACPI mode by Duncan Laurie · 11 years ago
  10. b40e444 baytrail: Enable panel and set timings by Duncan Laurie · 11 years ago
  11. 8b120a8 baytrail: allow SD card controller capabilities overrides by Aaron Durbin · 11 years ago
  12. 8cbf47f baytrail: add lpe codec clock configuration by Aaron Durbin · 11 years ago
  13. ae31f7d baytrail: pcie: Root port initialization by Aaron Durbin · 11 years ago
  14. 3c9f174 baytrail: Add EHCI initialization by Duncan Laurie · 11 years ago
  15. f81a91a baytrail: Add XHCI initialization by Duncan Laurie · 11 years ago
  16. 1dbd0e2 baytrail: Add SATA driver by Shawn Nematbakhsh · 11 years ago
  17. 9a7d7bc baytrail: add initial support by Aaron Durbin · 11 years ago