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review.coreboot.org / coreboot / 59be62480e2b9f51a66b5da3d552ae47425db9c6 / src / drivers / intel / fsp1_1 / ramstage.c
  1. 59be624 intel/fsp1.1: Mark graphics init done after SiliconInit phase by Duncan Laurie · 8 years ago
  2. cff5f09 drivers/intel/fsp1_1: Make fsp_run_silicon_init public by Lee Leahy · 9 years ago
  3. 7e7a4df lib: remove assets infrastructure by Aaron Durbin · 9 years ago
  4. fb50983 intel/fsp: Add post codes for FSP phases by Duncan Laurie · 9 years ago
  5. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  6. 94b856e FSP 1.1: Move common FSP code by Lee Leahy · 9 years ago[Renamed (98%) from src/soc/intel/common/fsp_ramstage.c]
  7. 5d6f0f9 soc/intel/common: use prog_locate() for finding fsp.bin by Aaron Durbin · 9 years ago
  8. 37a5d15 cbfs: add struct cbfsf by Aaron Durbin · 9 years ago
  9. 789f2b6 fsp1_1: provide binding to UEFI version by Aaron Durbin · 9 years ago
  10. 41c003c soc/intel/common/fsp_ramstage.c: Don't die when printing HOB info by Alexandru Gagniuc · 9 years ago
  11. c43d417 intel/common: fix stage_cache_external_region() by Aaron Durbin · 9 years ago
  12. abf87a2 intel/common: use external stage cache for fsp_ramstage by Aaron Durbin · 9 years ago
  13. 22ea007 fsp1_1: fsp_relocate: use struct region_device and struct prog by Aaron Durbin · 9 years ago
  14. 39bdb0b intel/common: use acpi_is_wakeup_s3() in fsp_ramstage.c by Aaron Durbin · 9 years ago
  15. 0946ec3 Intel Common SOC: Add romstage support by Lee Leahy · 9 years ago