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northbridge
56abd4d
nb/intel/sandybridge/raminit: always use mrccache
by Patrick Rudolph
· 8 years ago
5a57725
Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed"
by Timothy Pearson
· 8 years ago
ba817d0
nb/amd/mct_ddr3: Reenable sync flood after ECC init
by Timothy Pearson
· 8 years ago
1d9370b
nb/amd/mct_ddr3: Add MCE reporting logic
by Timothy Pearson
· 8 years ago
49e917b
nb/amd/amdfam10: Only flag machine check exception if valid bit is set
by Timothy Pearson
· 8 years ago
c5c3d76
nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform level
by Timothy Pearson
· 8 years ago
31d1959
nb/intel/sandybridge/raminit: die in toplevel function
by Patrick Rudolph
· 8 years ago
24a845b
nb/intel/sandybridge/raminit: prepare raminit for fallback
by Patrick Rudolph
· 8 years ago
7123e2e
nb/amd/mct_ddr3: Fix revision mask for DR processors
by Timothy Pearson
· 8 years ago
b3ddf83
nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
by Timothy Pearson
· 8 years ago
c00f4d6
nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs
by Timothy Pearson
· 8 years ago
c094d99
nb/amd/mct_ddr3: Disable MCE framework during DRAM training
by Timothy Pearson
· 8 years ago
f961bec
nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed
by Timothy Pearson
· 8 years ago
33aaa92
northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity)
by Damien Zammit
· 9 years ago
27e085a
nb/intel/sandybridge/raminit: move ram training into seperate function
by Patrick Rudolph
· 8 years ago
735ecce
nb/intel/sandybridge/raminit: move dimm_info into ramctr_timing
by Patrick Rudolph
· 8 years ago
e2e0057
nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D()
by Timothy Pearson
· 8 years ago
ec38c3d
nb/amd/amdmct: Select max_lanes based on ECC presence or absence
by Damien Zammit
· 9 years ago
54accfe
nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values
by Timothy Pearson
· 8 years ago
f1d807c
nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_SW_Fam15()
by Timothy Pearson
· 8 years ago
f7d4f73
nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set
by Timothy Pearson
· 8 years ago
264bf0b
cpu/x86/mtrr: move cache_ramstage() to its only user
by Aaron Durbin
· 8 years ago
bc5ad10
nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training
by Timothy Pearson
· 8 years ago
2510e2a
northbridge/intel/i3100: Unify UDELAY selection
by Stefan Reinauer
· 8 years ago
e3fd63f
northbridge/intel/i82810: Unify UDELAY selection
by Stefan Reinauer
· 8 years ago
63db614
northbridge/intel/i82830: Unify UDELAY selection
by Stefan Reinauer
· 8 years ago
2d987fe
nb/amd/mct_ddr3: Consolidate duplicated code
by Timothy Pearson
· 8 years ago
92fc072
northbridge/intel: move mrccache.c of sandybridge + haswell to common
by Alexander Couzens
· 8 years ago
81c5c76
northbridge/intel: move mrc_cache definition into a common header
by Alexander Couzens
· 8 years ago
f0ab23c
nortbridge/sandybridge/mrccache: parse the return code of flash->write
by Alexander Couzens
· 8 years ago
10d6fce
nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15
by Timothy Pearson
· 8 years ago
ed85f61
nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetch
by Timothy Pearson
· 8 years ago
2e1f731
nb/amd/mct_ddr3: Require minumum training quality for both read and write
by Timothy Pearson
· 8 years ago
50583f0
nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency
by Timothy Pearson
· 8 years ago
8eb221d
nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks
by Timothy Pearson
· 8 years ago
bbfcf62
nb/amd/mct_ddr3: Restore previous DQS delay values on failed loop
by Timothy Pearson
· 8 years ago
c7a1a3e
northbridge/i945/gma: Re-enable NVRAM tft_brightness
by Alexander Couzens
· 8 years ago
3d840d0
northbridge/intel/i440bx: Unify UDELAY selection
by Stefan Reinauer
· 8 years ago
0819a47
northbridge/intel/gm45: Use TSC for ramstage timer per default
by Stefan Reinauer
· 8 years ago
8e7928a
sandybridge/gma_lvds: support both Sandy&Ivy on one board
by Iru Cai
· 9 years ago
b97009e
nb/intel/sandybridge/raminit: Fill SMBIOS type17 info
by Patrick Rudolph
· 8 years ago
9f3f915
nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk
by Patrick Rudolph
· 9 years ago
77e45d3
nb/intel/sandybridge/raminit: Make discover_timC_write non cyclic
by Patrick Rudolph
· 8 years ago
d7ee9dd
northbridge/intel: add missing #include guards
by Iru Cai
· 8 years ago
d912f1d
nb/intel/sandybridge/raminit: Adjust timB to prevent overflow
by Patrick Rudolph
· 9 years ago
0e92bb0
tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"
by Denis 'GNUtoo' Carikli
· 8 years ago
bd1fdc6
nb/intel/sandybridge/raminit: Add XMP support
by Patrick Rudolph
· 9 years ago
41462bd
nb/amd/amdmct: Add socket specific configuration for FM2
by Damien Zammit
· 9 years ago
a649a54
nb/intel/sandybridge/raminit: Improve logging
by Patrick Rudolph
· 9 years ago
e4f9d5c
nb/intel/sandybridge: Start PEG link training
by Patrick Rudolph
· 9 years ago
e8e66f4
southbridge/intel/bd82x6x: Use common gpio.c
by Patrick Rudolph
· 9 years ago
0188b13
nb/intel/sandybridge/raminit: Add shift offset
by Patrick Rudolph
· 9 years ago
bd82d18
sandybridge: Always include MRC if not using native RAM init.
by Vladimir Serbinenko
· 9 years ago
144eea0
Make MRC vs native a config rather than making a separate chipset for it.
by Vladimir Serbinenko
· 9 years ago
ffbb3c0
Merge sandy/ivybridge romstage flow for MRC and non-MRC.
by Vladimir Serbinenko
· 9 years ago
59ff340
Kconfig: Move defaults for CBFS_SIZE
by Martin Roth
· 9 years ago
b2eea81
sandybridge: Set all native gfx-related options in northbridge code.
by Vladimir Serbinenko
· 9 years ago
609bd94
ivy: Add a possiblity for mainboard early init.
by Vladimir Serbinenko
· 9 years ago
2dc15e9
Revert "northbridge/intel/peg: Disable unused ports"
by Nico Huber
· 9 years ago
fec8872
nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h
by Timothy Pearson
· 9 years ago
3168236
nb/amd/mct_ddr3: Work around RDIMM training failure
by Timothy Pearson
· 9 years ago
0e06f5b
northbridge/intel/peg: Disable unused ports
by Patrick Rudolph
· 9 years ago
a1c3bed
nb/intel/sandybridge/raminit: Fix two dimms per channel
by Patrick Rudolph
· 9 years ago
2f91403
src: Fix various spelling and whitespace issues.
by Martin Roth
· 9 years ago
b410d26
nb/amd/amdmct/mct_ddr3: Save and restore SkewMemClk for S3 resume
by Timothy Pearson
· 9 years ago
448e386
drivers/pc80: Add PS/2 mouse presence detect
by Timothy Pearson
· 9 years ago
3141eac
Revert "northbridge/intel/sandybridge: Fix random raminit failures"
by Vladimir Serbinenko
· 9 years ago
8e9106d
nb/amdmct/mct_ddr3: Enable mainboard voltage set
by Timothy Pearson
· 9 years ago
71f8641
cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systems
by Timothy Pearson
· 9 years ago
5680faf
nb/intel/x4x: Move to early cbmem
by Damien Zammit
· 9 years ago
216fc50
nb/intel/x4x: Cleanup gma.c
by Damien Zammit
· 9 years ago
d63115d
nb/intel/x4x: Tidy up raminit and fix msbpos() function
by Damien Zammit
· 9 years ago
fe9876a
nb/intel/x4x: Tidy up northbridge
by Damien Zammit
· 9 years ago
9fb08f5
nb/intel/x4x: Fix memory hole with both channels populated
by Damien Zammit
· 9 years ago
23cc9b0
via/cx700: Use zeroptr over 0
by Patrick Georgi
· 9 years ago
51fdb92
nb/intel/pineview: Native VGA init (CRT)
by Damien Zammit
· 9 years ago
2cfab90
nb/intel/pineview: Increase MMCONF decoding to 256 busses
by Damien Zammit
· 9 years ago
db84a99
nb/amd/mct_ddr3: Properly set MR0 WR value
by Timothy Pearson
· 9 years ago
ad9a2bb
nb/amd/mct_ddr3: Add additional verbose-level debug statements
by Timothy Pearson
· 9 years ago
2d500ba
nb/amd/mct_ddr3: Update drive strength configuration
by Timothy Pearson
· 9 years ago
a2df081
northbridge/amd/amdmct/mct_ddr3: Enable fast refresh on ETR devices
by Timothy Pearson
· 9 years ago
6aa6eab
northbridge/amd/amdmct: Add termination and timing values for C32 sockets
by Timothy Pearson
· 9 years ago
19ce16a
northbridge/amd/amdfam10: Update DRAM speed limits for C32 sockets
by Timothy Pearson
· 9 years ago
02f4764
nb/intel/pineview: Use macro names for memory base registers
by Damien Zammit
· 9 years ago
f564606
nb/intel/pineview: Fix decode_pciebar()
by Damien Zammit
· 9 years ago
fd277d8
header files: Fix guard name comments to match guard names
by Martin Roth
· 9 years ago
7e513d1
intel/sandybridge/raminit: fix ODT setting
by Patrick Rudolph
· 9 years ago
b851cc6
nb/intel/gm45: Backport configuration of panel power timings
by Nico Huber
· 9 years ago
c3571da
nb/intel/gm45: Drop unnecessary panel power handling
by Nico Huber
· 9 years ago
a20ac2f
tree: drop last paragraph of GPL copyright header from new files
by Martin Roth
· 9 years ago
a696ae7
intel/northbridge/sandy: raminit code cleanup
by Patrick Rudolph
· 9 years ago
cbe3892
northbridge/intel/x4x: clean up includes
by Martin Roth
· 9 years ago
ee352cd
nb/intel/gm45: Convert gma.c to `if (IS_ENABLED(` style
by Nico Huber
· 9 years ago
2ed0aa2
Correct some common spelling mistakes
by Martin Roth
· 9 years ago
bb85f9e
Revert "AMD OemS3Save: refactor for Merlin Falcon"
by Kyösti Mälkki
· 9 years ago
5aaeb27
nb/intel/gm45: Export low-power and (SFF) options
by Nico Huber
· 9 years ago
4b513a6
northbridge/intel/x4x: Native raminit
by Damien Zammit
· 9 years ago
8a13743
x86 chipsets: Link non-code flow CHIPSET_BOOTBLOCK_INCLUDE files
by Alexandru Gagniuc
· 9 years ago
43a1f78
northbridge/intel/x4x: Intel 4-series northbridge support
by Damien Zammit
· 9 years ago
1eaaa0e
southbridge/amd/sr5650: Add MCFG ACPI table support
by Timothy Pearson
· 9 years ago
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