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review.coreboot.org / coreboot / 45d4b17f5e05cd493f19e69900a38ac805eb63b5 / src / northbridge / intel / sandybridge / romstage.c
  1. 45d4b17 nb/intel/sandybridge: Move southbridge code to bd82x6x by Patrick Rudolph · 5 years ago
  2. e2f0a5f sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB by Patrick Rudolph · 5 years ago
  3. 5d1f9a0 Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX) by Julius Werner · 5 years ago
  4. a1e22b8 src: Use 'include <string.h>' when appropriate by Elyes HAOUAS · 5 years ago
  5. 74aa99a src: Drop unused '#include <halt.h>' by Elyes HAOUAS · 5 years ago
  6. f1b58b7 device/pci: Fix PCI accessor headers by Kyösti Mälkki · 5 years ago
  7. 4513020 cpu/intel: Use the common code to initialize the romstage timestamps by Arthur Heymans · 6 years ago
  8. f765d4f src: Remove unneeded include <lib.h> by Elyes HAOUAS · 6 years ago
  9. 74203de intel/sandybridge: Don't hardcode platform type by Patrick Rudolph · 7 years ago
  10. db70f3b drivers/tpm: Add TPM ramstage driver for devices without vboot. by Philipp Deppenwiese · 6 years ago
  11. 21b71ce6 src/nb: Fix non-local header treated as local by Elyes HAOUAS · 6 years ago
  12. c07f8fb security/tpm: Unify the coreboot TPM software stack by Philipp Deppenwiese · 6 years ago
  13. ff4025c sb/intel/bd82x6x: Reduce function-disable mess by Nico Huber · 7 years ago
  14. d88fb36 security/tpm: Change TPM naming for different layers. by Philipp Deppenwiese · 7 years ago
  15. 64e2d19 security/tpm: Move tpm TSS and TSPI layer to security section by Philipp Deppenwiese · 7 years ago
  16. 5c31af8 nb/intel/sandybridge/romstage: Use register name by Patrick Rudolph · 7 years ago
  17. 128c104 nb/intel: Fix some spelling mistakes in comments and strings by Martin Roth · 8 years ago
  18. 75d139b intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP by Kyösti Mälkki · 8 years ago
  19. 0e92bb0 tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))" by Denis 'GNUtoo' Carikli · 8 years ago
  20. e8e66f4 southbridge/intel/bd82x6x: Use common gpio.c by Patrick Rudolph · 8 years ago
  21. 144eea0 Make MRC vs native a config rather than making a separate chipset for it. by Vladimir Serbinenko · 8 years ago
  22. ffbb3c0 Merge sandy/ivybridge romstage flow for MRC and non-MRC. by Vladimir Serbinenko · 8 years ago
  23. 609bd94 ivy: Add a possiblity for mainboard early init. by Vladimir Serbinenko · 8 years ago
  24. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  25. ecf2eb4 sandybridge ivybridge: Treat native init as first class citizen by Alexandru Gagniuc · 9 years ago[Renamed from src/northbridge/intel/sandybridge/romstage_native.c]
  26. 9796f60 coreboot: move TS_END_ROMSTAGE to one spot by Aaron Durbin · 9 years ago
  27. ed54cc7 sandybridge native: Add call to TPM code. by Vladimir Serbinenko · 9 years ago
  28. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  29. 8b2c8f1 sandybridge/raminit: Get max mem clock from devicetree by Alexandru Gagniuc · 9 years ago
  30. bd79c5e Replace hlt() loops with halt() by Patrick Georgi · 10 years ago
  31. 33b535f sandy/ivy/nehalem: Remerge interrupt handling by Vladimir Serbinenko · 10 years ago
  32. fa1d688 sandy/ivy native: dedup romstage.c main() by Vladimir Serbinenko · 10 years ago