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review.coreboot.org / coreboot / 43b7f416783ccc98952a4eb5f9274907442b03e5 / src / soc / intel / alderlake / fsp_params.c
  1. 43b7f41 src: Make PCI ID define names shorter by Felix Singer · 2 years, 4 months ago
  2. 02967e6 soc/intel/alderlake: Fix function pointer type by Arthur Heymans · 2 years, 5 months ago
  3. a6d642f soc/intel/alderlake: Enable eMMC based on dev enabled by Krishna Prasad Bhat · 2 years, 6 months ago
  4. c6b65c1 soc/intel/alderlake: Enable USB2 port reset message on Type-C ports by Anil Kumar · 2 years, 5 months ago
  5. 393b093 soc/intel/alderlake: Skip FSP to unlock GPIO Pads by Subrata Banik · 2 years, 6 months ago
  6. 2abb826 src: Remove unused <cbfs.h> by Elyes HAOUAS · 2 years, 6 months ago
  7. 577afe6 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04 by Nick Vaccaro · 2 years, 6 months ago
  8. f944052 soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs by Tim Wawrzynczak · 2 years, 7 months ago
  9. ea1bb5f soc/intel/alderlake: Add TDP to give correct VR configuration by Curtis Chen · 2 years, 8 months ago
  10. 0c54461 soc/intel/alderlake: Add ADLP 4+4+2 power configurations by Curtis Chen · 2 years, 8 months ago
  11. 3160595 soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL-M by Bora Guvendik · 2 years, 10 months ago
  12. c510346 soc/intel/alderlake: Add Acoustic noise mitigation UPDs by Wisley Chen · 2 years, 8 months ago
  13. d0cef2a soc/intel/alderlake: Enable Intel FIVR RFI settings by Wisley Chen · 2 years, 8 months ago
  14. fbf874f soc/intel/alderlake: Fix wrong FIVR configs assignment by Bora Guvendik · 2 years, 9 months ago
  15. 0e90580 soc/intel: transition full control over PM Timer from FSP to coreboot by Michael Niewöhner · 2 years, 10 months ago
  16. 291294d soc/intel/alderlake: fix NULL pointer dereference by Selma Bensaid · 2 years, 9 months ago
  17. d6da4ef soc/intel/alderlake: Skip setting D0I3 bit for HECI devices by Subrata Banik · 2 years, 9 months ago
  18. 4a48dbe src/soc/intel/alderlake: Add PsysPmax setting by Ryan Lin · 2 years, 9 months ago
  19. 697d6a8 soc/intel/alderlake: Add ADLP 242 power configurations by Tracy Wu · 2 years, 9 months ago
  20. ab0e081 soc/intel/alderlake: Add support for power cycle and SLP signal duration by Tim Wawrzynczak · 2 years, 10 months ago
  21. 7b523a4 soc/intel/alderlake: Use intel_microcode_find() to locate ucode.bin by Subrata Banik · 2 years, 10 months ago
  22. eafca1f soc/intel/alderlake: Switch to using device pointers by Furquan Shaikh · 2 years, 10 months ago
  23. 298b359 drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling method by Subrata Banik · 2 years, 10 months ago
  24. e2b8f30 soc/intel/alderlake: Set LpmStateEnableMask UPD by Tim Wawrzynczak · 3 years ago
  25. 091dfa1 soc/intel/alderlake: Lock PAM registers in finalize by Tim Wawrzynczak · 2 years, 11 months ago
  26. f9d7dc7 soc/intel/alderlake: Clean up FSP chipset lockdown configuration by Felix Singer · 3 years, 2 months ago
  27. c6d7166 soc/intel/alderlake: Configure the SKU specific parameters for VR domains by V Sowmya · 3 years ago
  28. 458708f soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL by V Sowmya · 3 years ago
  29. bc35bed soc/intel/*: Allow configuring 8254 timer via CMOS by Sean Rhodes · 3 years ago
  30. 87685c5 soc/intel/alderlake: Make use of `cpu/intel/cpu_ids.h' by Subrata Banik · 3 years ago
  31. 82225b8 soc/intel/alderlake: Add (and fix) devices in IRQ table by Tim Wawrzynczak · 3 years ago
  32. af42906 soc/intel/alderlake: Set max Pkg C-states to Auto by V Sowmya · 3 years, 1 month ago
  33. 418d37e soc/intel/alderlake: Add support to update the FIVR configs by V Sowmya · 3 years, 1 month ago
  34. 421ce56 soc/intel/alderlake: Add USB TCSS enablement by Bernardo Perez Priego · 3 years, 1 month ago
  35. 844dcb3 soc/intel/alderlake: Enable energy efficiency turbo mode by V Sowmya · 3 years, 1 month ago
  36. c7cfe0b soc/intel: Refactor `xdci_can_enable()` function by Angel Pons · 3 years, 1 month ago
  37. c0e82e7 soc/intel/alderlake: Send End-of-Post message to CSE by Tim Wawrzynczak · 3 years, 1 month ago
  38. 43607e4 soc/intel/alderlake: Enable support for common IRQ block by Tim Wawrzynczak · 3 years, 2 months ago
  39. 6464c2a soc/intel/alderlake: Fix the typo for FSP_S_CONFIG param by V Sowmya · 3 years ago
  40. b03cadf soc/intel/alderlake: Refactor soc_silicon_init_params function by Subrata Banik · 3 years, 1 month ago
  41. c0983c9 soc/intel/alderlake: Rename FSP_S_CONFIG variable from params to s_cfg by Subrata Banik · 3 years, 1 month ago
  42. 6f1cb40 soc/intel/alderlake: Refactor platform_fsp_silicon_init_params_cb function by Subrata Banik · 3 years, 1 month ago
  43. e633804 soc/intel/alderlake: Use devfn_disable() function for XDCI by Subrata Banik · 3 years, 1 month ago
  44. 095f97b soc/intel/alderlake: Add TBT PCIe root ports enablement by Bernardo Perez Priego · 3 years, 2 months ago
  45. 50134ec soc/intel/alderlake: Make use of is_devfn_enabled() function by Subrata Banik · 3 years, 1 month ago
  46. b9b6f4d soc/intel: Drop unused lpss functions by Furquan Shaikh · 3 years, 1 month ago
  47. 8e7facf soc/intel/alderlake: mb/intel/sm: Add tcss code by Deepti Deshatty · 3 years, 2 months ago
  48. 6935350 soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC by Maulik V Vaghela · 3 years, 3 months ago
  49. bc1941f soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entry by Cliff Huang · 3 years, 5 months ago
  50. 812b54e soc/intel/alderlake: Set LidStatus UPD if RUN_FSP_GOP selected by Ronak Kanabar · 3 years, 5 months ago
  51. 5b302b2 soc/intel/alderlake: Refactor PCIE port config by Eric Lai · 3 years, 7 months ago
  52. 85144d9 soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs by Subrata Banik · 3 years, 6 months ago
  53. 99289a8 soc/intel/alderlake: Update CPU microcode patch base address/size by Subrata Banik · 3 years, 7 months ago
  54. 2871e0e soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage by Subrata Banik · 3 years, 9 months ago